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resources:eval:user-guides:spi [09 May 2022 18:20] – [AD5758 Address Bits] Erlandas Petkevicius | resources:eval:user-guides:spi [18 May 2022 13:59] (current) – final edit valerie hamilton | ||
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- | ===== Serial Peripheral Interface on AD5758 | + | ==== Using the Serial Peripheral Interface on the AD5758 ==== |
+ | <WRAP info> | ||
+ | The **AD5758/ | ||
+ | </ | ||
- | ==== Slip Bit ==== | + | The AD5758 |
- | A further enhancement to the robustness of the interface | + | |
- | addition of the slip bit. The MSB of the SPI frame must equal | + | |
- | the inverse | + | |
- | SLIPBIT_ERROR bit in the DIGITAL_DIAG_RESULTS register | + | |
- | is asserted. | + | |
+ | === SPI Modes === | ||
+ | SPI has 4 modes that it operates in. The CPOL bit sets the clocks polarity during the idle state. The CPHA bit selects the clock phase. For mode 0 and mode 1, the idle clock state is low. For mode 2 and mode 3, the idle clock state is high. The CPOL and CPHA bits decide on which edge the data is sampled and shifted. The Mode Table below demonstrates SPI modes. The AD5758 (and all other generics listed in the INFO) can be used in either mode 1 or mode 2. | ||
- | ==== AD5758 Address Bits ==== | + | ===SPI Mode Table=== |
- | The AD5758 address pins (AD0 and AD1) are used in | + | ^ SPI Mode ^ CPOL ^ CPHA |
- | conjunction with the address bits within | + | | 0 | 0 |
- | addressed by the system controller. With the two address pins, | + | | 1 | 0 |
- | up to four devices can be independently addressed | + | | 2 | 1 |
+ | | 3 | 1 | ||
- | ==== Register Address Bits ==== | ||
- | ==== Data Bits ==== | + | === SPI Cyclic Redundancy Check (CRC)=== |
+ | To verify that data has been received correctly in noisy environments, | ||
+ | *< | ||
+ | This sequence is added to the end of the 24 bit data-word, and 32 bits are sent to the AD5758 before taking SYNC high. | ||
- | + | If the CRC check is valid, | |
- | ==== SPI Cyclic Redundancy Check ==== | + | the selected register. If the CRC check fails, the data is ignored |
- | To verify that data has been received correctly in noisy environments, | + | the SPI_CRC_ERR |
- | The device controlling the AD5758 generates an 8-bit frame | + | transmission and receipt of data packets. The CRC is enabled by default |
- | check sequence using the following polynomial: | + | |
- | C(x) = x8 + x2 + x1 + 1 | + | |
- | This sequence | + | |
- | are sent to the AD5758 before taking SYNC high. | + | |
- | + | ||
- | If the SPI_CRC_EN | + | |
supply a frame of exactly 32 bits wide that contains the 24 data bits | supply a frame of exactly 32 bits wide that contains the 24 data bits | ||
- | and 8-bit CRC. If the CRC check is valid, the data is written to | + | and 8-bit CRC for the first SPI write. To disable |
- | the selected register. If the CRC check fails, the data is ignored, | + | |
- | the FAULT pin goes low and the FAULT pin status bit and the | + | |
- | digital diagnostic status bit (DIG_DIAG_STATUS) | + | |
- | register | + | |
- | DIGITAL_DIAG_RESULTS register reveals that the | + | |
- | SPI_CRC_ERR bit is also set. This register is a per bit, write to | + | |
- | clear register (see the Sticky Diagnostic Results Bits section); | + | |
- | therefore, the SPI_CRC_ERR bit can be cleared by writing a 1 to | + | |
- | Bit D0 of the DIGITAL_DIAG_RESULTS register. Doing so | + | |
- | clears the SPI_CRC_ERROR bit and causes the FAULT pin to | + | |
- | return high (assuming that there are no other active faults). | + | |
- | When configuring the FAULT_PIN_CONFIG register, the user | + | |
- | can decide whether the SPI CRC error affects the FAULT pin. | + | |
- | See the FAULT Pin Configuration Register section for further | + | |
- | details. The SPI CRC feature can be used for both the | + | |
- | transmission and receipt of data packets. | + | |
- | + | ||
- | ==== SPI Modes ==== | + | |
- | SPI has 4 modes that it operates in. CPOL bit sets the clocks polarity during the idle state. The CPHA bit selects the clock phase. For mode 0 and mode 1, the idle clock state is low. For mode 2 and mode 3, the idle clock state is high. CPOL and CPHA bits decide on which edge is the data sampled and shifted. Table 1 below demonstrates SPI modes. | + | |
- | + | ||
- | {{table_1.png? | + | |
- | + | ||
- | //Table 1: 4 SPI Modes | + | |
- | // | + | |
- | + | ||
- | ==== Writes | + | |
- | Figure 1 below shows an example of a flowchart that performs writes to registers. | + | |
- | {{flowchart.png}} | + | |
- | + | ||
- | //Figure 1: Example Flowchart | + | |
- | // | + | |
- | + | ||
- | === Reset === | + | |
- | Before writing to registers, AD5758 must be reset either by hardware or software. Figure 2 below shows SPI code when AD5758 resets. The top signal is clock frequency. The clock performs 32 oscillations when the green signal /SYNC goes low. Yellow signal is SDI signal. The SPI protocol performs writes to the SDI. From MSB to LSB, the first 3 bits is AD5758 address. Next 5 bits are register address. Next 16 bits is the data sent to the register address that configures that register. Last 8 bits are CRC code. | + | |
- | + | ||
- | The reset function is in register address 0x08. This is a key register that performs reset by writing 0x15FA to the key register. | + | |
- | {{reset.png? | + | |
- | + | ||
- | //Figure 2: Reset Writes | + | |
- | // | + | |
- | === Clear RESET_OCCURED Bit === | + | |
- | Once reset has occurred, RESET_OCCURED bit needs to be cleared that is the 13th bit in DIGITAL_DIAG_RESULTS. Figure 3 below demonstrates 0x2000 written to register 0x14 to clear RESET_OCCURED bit. | + | |
- | {{rst_occ.png? | + | |
- | //Figure 3: RESET_OCCURED Bit Being Cleared | + | ===Writing to a Register=== |
- | // | + | |
- | === CLKOUT Configuration === | + | As shown in the SPI Write Frame table, every SPI write frame contains a slip bit, two address bits, a register |
- | Default settings are left on 0x09 register. | + | |
- | {{clkout_config.png}} | + | ===SPI Write Frame=== |
+ | ^ D31 ^ D30: | ||
+ | | Slip Bit | Address Bits | Register Address | ||
- | //Figure 4: Default GP_CONFIG1 Register Settings | + | With CRC enabled (default state), the input shift register is 32 bits wide. Data is loaded into the device MSB first, under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If CRC is disabled, the serial interface is reduced to 24 bits; a 32-bit frame is still accepted but the last 8 bits are ignored. \\ |
- | // | + | |
- | === DC to DC Conversion Settings | + | ===Reading a Register=== |
- | Default settings are left on 0x0c register. | + | The default mode for reading back a register |
- | {{dcdc.png}} | + | ===SPI Read Frame=== |
+ | ^ D31: | ||
+ | | 10 | Fault Pin Status | ||
- | //Figure 5: Default DCDC_CONFIG2 Register Settings | ||
- | // | ||
- | DC to DC conversion mode is left default. Figure 6 below shows 0x0000 written | + | === Performing a Software Reset === |
+ | Before initially configuring the device, it is good practice to perform either a hardware or software reset. A software reset is performed by writing 2 keys (0x15FA and 0xAF51) respectively | ||
- | {{dcdc2.png}} | + | Figures 1 and 2 show the first and second software reset key writes. The first write of 0x8815FAA4 can be decoded as |
- | //Figure 6: Default DCDC_CONFIG1 | + | ^ D31 ^ D30:D29 |
- | // | + | | Slip Bit | Address Bits | |
+ | | 1 | 00 | 0x08 (01000) | ||
- | === Disabled DAC Output === | + | For the second write the data has changed to 0xFA51 and the CRC changed to 0x31. |
- | DAC output is disabled on default in DAC_CONFIG register. This is shown in figure 7 below. | + | |
- | {{dac_out_dis.png}} | ||
- | //Figure 7: DAC Output Disabled | + | The oscilloscope plots below show each of the 4 SPI wire data:\\ |
- | // | + | <fc # |
+ | <fc # | ||
+ | <fc # | ||
+ | <fc # | ||
+ | **In the following examples the software driver is configured for SPI mode 1 and the CRC is enabled.**\\ \\ | ||
- | Since DAC output is disabled, 0x0000 is written to DAC_INPUT register as shown in figure 8 below. | + | {{ : |
+ | <WRAP centeralign> | ||
+ | //Figure 1 Software Reset Key1 Write 0x8815FAA4// | ||
+ | </ | ||
- | {{dac_input.png}} | + | {{ : |
+ | <WRAP centeralign> | ||
+ | //Figure 2 Software Reset Key2 Write 0x88AF5131// | ||
+ | </ | ||
- | //Figure | + | Figure |
- | // | + | |
- | Writing 0x1DAC to 0x07 register performs a software LDAC update on the device matching the ADDRESS bits within the SPI frame. If | + | {{ : |
- | the GLOBAL_SW_LDAC bit in the GP_CONFIG2 register is set, the AD0 and AD1 bits are ignored and all devices sharing the same SPI | + | <WRAP centeralign> |
- | bus are updated via the SW_LDAC | + | //Figure 3 Two Stage Readback |
+ | </ | ||
- | {{1dac.png}} | ||
- | // | + | {{ : |
- | // | + | <WRAP centeralign> |
+ | // | ||
+ | </ | ||
+ | {{ :resources: | ||
+ | <WRAP centeralign> | ||
+ | //Figure 5 Two Stage Readback command - second frame write 0x8000000B (including SDO data 0x94A0001A)// | ||
+ | </ | ||
- | DAC output is enabled by writing 0x0c40 to 0x06 register address. | ||
- | {{dac_out_en.png}} | + | === Calibration Memory Refresh === |
+ | After performing a software or hardware reset the next write **must** be a calibration memory refresh. The refresh is performed by writing the key 0xFCBA to the key register (address 0x08). The calibration memory refresh SPI write is 0x88FCBA9D. | ||
- | //Figure 10: DAC output enabled in DAC_CONFIG register | + | ===Disabling CRC=== |
- | // | + | After performing a calibration refresh the CRC can be disabled if desired. The command to disable the CRC is Figure 4 shows the SPI write to clear the reset occurred bit. The SPI write to disable the CRC is 0x50005CB7. |
- | To test and see if DAC output is enabled, 0xaaaa | + | ===Clearing Reset Occurred=== |
+ | After performing a calibration refresh the device can now be configured as required. The reset occurred bit (Bit 13) in the digital diagnostic results register (Address 0x14) is a logic high and should be cleared. To clear the bit a " | ||
- | {{dac_input_aaaa.png}} | ||
- | //Figure 11: 0xaaaa is written to DAC_INPUT register to test and see if DAC output is enabled | ||
- | // | ||
+ | |||