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resources:eval:user-guides:rf-trx-vcxo-and-profiles [03 Jan 2021 21:46] – fix links Robin Getzresources:eval:user-guides:rf-trx-vcxo-and-profiles [04 Mar 2022 13:17] – [ERROR: 321: Tx Profile IQrate and filter settings are not possible with current CLKPLL frequency] Michael Hennerich
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 There are limitations with the default hardware configuration in the scenario where a user desired device frequencies are not related to the on-board 122.88MHz VCXO by a rational fraction. Examples of such device clock frequency are: 125MHz, 133.33MHz, 250MHz and 266.66MHz. The document below outlines these limitations as well as explains how they can be overcome with an AD9371 evaluation board hardware modification. Pretty much the same things also apply for all the other devices listed above. There are limitations with the default hardware configuration in the scenario where a user desired device frequencies are not related to the on-board 122.88MHz VCXO by a rational fraction. Examples of such device clock frequency are: 125MHz, 133.33MHz, 250MHz and 266.66MHz. The document below outlines these limitations as well as explains how they can be overcome with an AD9371 evaluation board hardware modification. Pretty much the same things also apply for all the other devices listed above.
  
-  * [[https://ez.analog.com/wide-band-rf-transceivers/design-support-ad9371/w/documents/10080/ad9371-evaluation-board-vcxo-selection | Evaluation-board-vcxo-selection]]+  * [[ez>wide-band-rf-transceivers/design-support-ad9371/w/documents/10080/ad9371-evaluation-board-vcxo-selection | Evaluation-board-vcxo-selection]]
  
 This page is supposed to be a system level addition to the aforementioned document with some extra tips and tricks. This page is supposed to be a system level addition to the aforementioned document with some extra tips and tricks.
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   * [[adi>static/imported-files/data_sheets/AD9528.pdf|AD9528 data sheet]]   * [[adi>static/imported-files/data_sheets/AD9528.pdf|AD9528 data sheet]]
   * [[adi>eval-ad9528|AD9528 Evaluation Board Software]]   * [[adi>eval-ad9528|AD9528 Evaluation Board Software]]
-  * [[http://wiki.analog.com/resources/eval/csg-evalsoftware-user-guide|Clock Generation and Distribution Evaluation Software User Guide]] +  * [[/resources/eval/csg-evalsoftware-user-guide|Clock Generation and Distribution Evaluation Software User Guide]] 
  
 <code> <code>
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 //adi,dig-clocks-clk-pll-hs-div = <0>;// //adi,dig-clocks-clk-pll-hs-div = <0>;//
 +
 +==== ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case () ====
 +
 +Can be caused by an invalid filter wizard profile.
 +Please see answer here: [[ez>linux-software-drivers/f/q-a/555532/qec-init/450766|Changing the VCXO 80 MHz ad9375]]
  
  
resources/eval/user-guides/rf-trx-vcxo-and-profiles.txt · Last modified: 14 Nov 2022 10:59 by Liviu-Mihai Iacob