This version is outdated by a newer approved version.
This version (19 Jan 2018 10:22) was approved by Alexandru Ardelean.The Previously approved version (27 Sep 2017 01:05) is available.
This version (19 Jan 2018 10:22) was approved by Alexandru Ardelean.The Previously approved version (27 Sep 2017 01:05) is available.This is an old revision of the document!
Table of Contents
FMC Carrier
Hardware
Rev C FMC Carrier
This is the Rev C schematic and layout files for the FMC carrier.
- Rev C Allegro Board File (This file is compressed). Get the Allegro FREE Physical Viewer (You need 16.6 or higher).
Trips and Tricks
External AD9361 reference clock via J1
An external Reference Clock can be supplied via J1. In order the switch the source the zynq-adrv9361-z7035.dtsi device tree needs to be modified.
clocks {
xo_40mhz_fixed_clk: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <40000000>;
clock-output-names = "XO_40MHz";
};
ad9361_clkin: clock@1 {
#clock-cells = <0>;
compatible = "gpio-gate-clock";
clocks = <&xo_40mhz_fixed_clk>;
enable-gpios = <&gpio0 105 1>; /* Set to 1 for extern AD9361_CLK */
clock-output-names = "ad9361_ext_refclk";
};
Option:
enable-gpios = <&gpio0 105 ACTIVE_LEVEL>;
ACTIVE_LEVEL:
0 (active high) use on-board XO
1 (active low) use external clock via J1
- Update the clock-frequency property with the exact frequency of the external supplied clock.
- Set enable-gpios = <&gpio0 105 1>
- Rebuild and install your modified device tree on the target
resources/eval/user-guides/pzsdr/carriers/fmc.1516353759.txt.gz · Last modified: 19 Jan 2018 10:22 by Alexandru Ardelean