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resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware [23 Feb 2018 23:37] – fixed some layout issues Jeff Watson | resources:eval:user-guides:high-temp:ev-ht-200cdaq1:firmware [01 Mar 2018 03:38] – added links to diagrams Jeff Watson | ||
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EV-HT-200CDAQ1 Firmware Flowchart | EV-HT-200CDAQ1 Firmware Flowchart | ||
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Parser Routine Flow | Parser Routine Flow | ||
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This section has tables showing the pins, peripherals and interrupts used in the project. | This section has tables showing the pins, peripherals and interrupts used in the project. | ||
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==== MCU Pin Use Table ==== | ==== MCU Pin Use Table ==== | ||
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The ADC servicing is done in the timer interrupt service routine. | The ADC servicing is done in the timer interrupt service routine. | ||
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Data collected from the ADC is stored in a dedicated 16kbyte (16,384) buffer that will later be sent out a UART port to a PC host. The buffer can be divided into segments for different ADC channels as set by the incoming command. | Data collected from the ADC is stored in a dedicated 16kbyte (16,384) buffer that will later be sent out a UART port to a PC host. The buffer can be divided into segments for different ADC channels as set by the incoming command. | ||
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The SPI clock is set to 25 MHz. This is half the MCU system clock and the fastest achievable SPI master clock from the VA10800. | The SPI clock is set to 25 MHz. This is half the MCU system clock and the fastest achievable SPI master clock from the VA10800. | ||
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==== Aligning CNV signals for ADC0 & ADC1 ==== | ==== Aligning CNV signals for ADC0 & ADC1 ==== | ||
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One of the sampling timing requirements is that the CNV signals for ADC0 and ADC1 being exactly aligned. | One of the sampling timing requirements is that the CNV signals for ADC0 and ADC1 being exactly aligned. | ||
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==== External Trigger Mode ==== | ==== External Trigger Mode ==== | ||
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The below diagram shows the priority hierarchy. | The below diagram shows the priority hierarchy. | ||
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Due to some inherent interrupt blocking of FreeRTOS during task changes, a conflict can arise when the ADCs are being converted very rapidly, under 4us. During an acquisition experiment with sampling rate under 4us, the RTOS is temporarily disabled. | Due to some inherent interrupt blocking of FreeRTOS during task changes, a conflict can arise when the ADCs are being converted very rapidly, under 4us. During an acquisition experiment with sampling rate under 4us, the RTOS is temporarily disabled. | ||
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==== Temperature and Vcc Calculation ==== | ==== Temperature and Vcc Calculation ==== | ||
- | The RTD data sheet contains a table with resistance values for every 1C. Firmware has created a linear interpolation conversion program for 5 different regions in the -55C | + | The RTD data sheet contains a table with resistance values for every 1°C. Firmware has created a linear interpolation conversion program for 5 different regions in the -55°C to 200°C |
Both the RTD and VCC calculations account for a voltage divider network. | Both the RTD and VCC calculations account for a voltage divider network. | ||
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===== Performance ===== | ===== Performance ===== | ||
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As shown in the below diagram, the fastest ADC sample rate using interrupt is 413 kHz which corresponds to 2.4ųs. | As shown in the below diagram, the fastest ADC sample rate using interrupt is 413 kHz which corresponds to 2.4ųs. | ||
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==== UART RX Performance ==== | ==== UART RX Performance ==== |