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| resources:eval:user-guides:circuits-from-the-lab:cn0585 [03 Oct 2023 15:47] – [Hardware Registration] Paul Blanchard | resources:eval:user-guides:circuits-from-the-lab:cn0585 [29 Jan 2024 18:28] (current) – Update CN0585 revB photo Xiaomeng Gao |
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| The [[ADI>CN0585|EVAL-CN0585-FMCZ]] Low Latency Development Kit (LLDK) board is a development board consisting of 4 x 16-bit ADC channels and 4 x 16-bit DAC channels that are interfaced with an FPGA through the FMC Low Pin Count (LPC) Connector. Current revision of [[ADI>CN0585|EVAL-CN0585-FMCZ]] is Rev B. [[ADI>CN0585|EVAL-CN0585-FMCZ]], [[adi>CN0584|EVAL-CN0584-EBZ]] and ZedBoard are connected together to build a development system setup as shown in Figure 1.{{:resources:eval:user-guides:circuits-from-the-lab:cn0585:setup_cn0585_diagram.png?nolink|}}. | The [[ADI>CN0585|EVAL-CN0585-FMCZ]] Low Latency Development Kit (LLDK) board is a development board consisting of 4 x 16-bit ADC channels and 4 x 16-bit DAC channels that are interfaced with an FPGA through the FMC Low Pin Count (LPC) Connector. Current revision of [[ADI>CN0585|EVAL-CN0585-FMCZ]] is Rev B. [[ADI>CN0585|EVAL-CN0585-FMCZ]], [[adi>CN0584|EVAL-CN0584-EBZ]] and ZedBoard are connected together to build a development system setup as shown in Figure 1.{{:resources:eval:user-guides:circuits-from-the-lab:cn0585:setup_cn0585_diagram.png?nolink|}}. |
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| //Figure 1. Development Platform Setup// | //Figure 1. Development Platform Setup (note current LLDK system has CN0585 revB board that has USB-C power supply)// |
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| The [[ADI>CN0585|EVAL-CN0585-FMCZ]] board provides a complete data acquisition and signal generation platform with onboard power rails, voltage monitoring, logic level translation, general purpose I/O, I2C, SPI, and an Analog Front End(AFE) board connector. | The [[ADI>CN0585|EVAL-CN0585-FMCZ]] board provides a complete data acquisition and signal generation platform with onboard power rails, voltage monitoring, logic level translation, general purpose I/O, I2C, SPI, and an Analog Front End(AFE) board connector. |
| The key performance benefit of the [[ADI>CN0585|EVAL-CN0585-FMCZ]] is the ability to perform a complete capture and conversion of precision analog input data in <70ns with the ADC module and generate a settled full-scale analog output in <200ns from initial data written to the DAC. | The key performance benefit of the [[ADI>CN0585|EVAL-CN0585-FMCZ]] is the ability to perform a complete capture and conversion of precision analog input data in <70ns with the ADC module and generate a settled full-scale analog output in <200ns from initial data written to the DAC. |
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| {{resources:eval:user-guides:circuits-from-the-lab:cn0585:cn0585_top.jpg?500|}} | {{ :resources:eval:user-guides:circuits-from-the-lab:cn0585:eval-cn0585-fmcz_top-web.jpg?400 |}} |
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| //Figure 2. EVAL-CN0585-FMCZ Board Top// | //Figure 2. EVAL-CN0585-FMCZ Board Top// |
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| {{resources:eval:user-guides:circuits-from-the-lab:cn0585:cn0585_bottom.jpg?300|}} | {{ :resources:eval:user-guides:circuits-from-the-lab:cn0585:eval-cn0585-fmcz_bottom-web.jpg?400 |}} |
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| //Figure 3. EVAL-CN0585-FMCZ Board Bottom// | //Figure 3. EVAL-CN0585-FMCZ Board Bottom// |
| ===== Reference Demos & Software ===== | ===== Reference Demos & Software ===== |
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| * [[.:cn0585:reference_hdl|Reference HDL Design]] | |
| * [[:resources:fpga:docs:axi_ad3552r| AXI_AD3552R IP core]] | * [[:resources:fpga:docs:axi_ad3552r| AXI_AD3552R IP core]] |
| * [[:resources:fpga:docs:axi_ltc2387| AXI_LTC2387 IP core]] | * [[:resources:fpga:docs:axi_ltc2387| AXI_LTC2387 IP core]] |
