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resources:eval:user-guides:circuits-from-the-lab:cn0577:hdl [16 Aug 2022 16:22] – Iulia Moldovanresources:eval:user-guides:circuits-from-the-lab:cn0577:hdl [22 Feb 2023 12:54] (current) – Add Circuit Note page Iulia Moldovan
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 ===== Introduction ===== ===== Introduction =====
  
-The [[ADI>CN0577]] is a low noise, high speed successive approximation register (SAR) ADC with a resolution of 16-/18-bit and sampling rate up to 15MSPS. +The [[ADI>CN0577]] provides an analog front-end and an FMC digital interface for [[adi>LTC2387-18|LTC2387-18]], its core. It is a low noise, high speed successive approximation register (SAR) ADC with a resolution of 18 bits and sampling rate up to 15MSPS.
  
-In order to support high speed operations while minimizing the number of data lines, a serial LVDS digital interface is used. It has a one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application, through setting a parameter.+CN0577 includes an on-board reference oscillator and a retiming circuit to minimize signal-to-noise ratio (SNR) degradation due to the FPGA additive jitter.
  
 +In order to support high speed operations while minimizing the number of data lines, a serial LVDS digital interface is used. It has a one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application, through setting a parameter. \\
 +
 +More details about ADI reference designs architecture [[:resources:fpga:docs:arch|here]].
  
 ===== Evaluation board ===== ===== Evaluation board =====
-  * [[ |CN0577 Circuit Note Page]] +  * [[adi>media/en/reference-design-documentation/reference-designs/cn0577.pdf |CN0577 Circuit Note Page]] 
-  * [[ |CN0577 wiki]]+  * [[adi>LTC2387-18|LTC2387-18]] chip
  
  
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 ===== HDL Design Description ===== ===== HDL Design Description =====
 +<note important>In the master version, the TWOLANES parameter is set to 1, so it works only in two-lane output mode.</note>
 +
 +<note important>The VADJ for the Zedboard must be set to 2.5V!</note>
 +
 +The PD and TESTPAT parameters are tied to GPIOs (33 and 32 respectively) so they can be configured by the software.
 +
 +The conversion starts when a rising edge is detected on the CNV signal. This signal is generated by the [[:resources:fpga:docs:axi_pwm_gen|AXI_PWM_GEN]] core, alongside with a clk_gate signal.
 +
  
-<WRAP center round todo 60%> 
 ==== Block Diagram ==== ==== Block Diagram ====
 +{{ :resources:eval:user-guides:circuits-from-the-lab:cn0577:cn0577_block_diagram.png?direct&600 |}}
 +
 +
 +==== Parameters ====
 +
 +The only parameter that can be changed so far, is ''TWOLANES''. It specifies whether the two-lane output mode is activated or not. When activated, the ADC outputs two bits at the same time, on DA+/DA- and DB+/DB-. When it is low, then DB+/DB- is disabled.
 +
 +By default, it is set to 1 [[repo>hdl/tree/master/projects/cn0577/zed/system_bd.tcl#L2|here]] and passed further through the board design file [[repo>hdl/tree/master/projects/cn0577/common/cn0577_bd.tcl#L19|here]].
 +
 +=== PL interrupts ===
 +
 +When developing the Linux software parts for an HDL project, the interrupts number to the PS have a different number in the software side.
 +More details [[:resources:fpga:docs:arch#interrupts|here]].
 +
 +^Interr. name ^HDL interr. ^Linux Zynq ^Actual Zynq ^
 +|  axi_ltc2387_dma  |  13  |  57  |  89  |
 +
 +=== GPIO signals ===
 +
 +PS7 EMIO offset = 54
 +
 +^GPIO HDL name   ^GPIO nb. ^HDL GPIO nb.^
 +| pd_cntrl | 87 | 33 |
 +| testpat_cntrl | 86 | 32 |
 +
 +
 +==== I/O Interface ====
 +
 +^ Interface ^ Pin ^ Type ^ Description ^
 +| **Core clock** ||||
 +|              | ''ref_clk_*'' | ''input'' | LVDS clock input |
 +|**LVDS ADC interface** ||||
 +|              | ''clk_*'' | ''output'' | LVDS output clock going to the chip, to serially shift out the conversion result |
 +|              | ''dco_*'' | ''input'' | LVDS data clock input |
 +|              | ''da_*'' | ''input'' | Serial LVDS data input |
 +|              | ''db_*'' | ''input'' | Serial LVDS data input |
 +|              | ''cnv_*'' | ''output'' | Conversion start LVDS |
 +|              | ''cnv_en'' | ''output'' | Conversion enable, used as clear signal for the retiming flop from the chip (see schematic)  |
 +|              | ''pd_cntrl'' | ''output'' | Powerdown control signal |
 +|              | ''testpat_cntrl'' | ''output'' | Enable for testing with a predefined pattern |
 +|              | ''twolanes_cntrl'' | ''output'' | Selection between one-lane mode and two-lane mode. Default it is 1 |
 +
 +
 +==== Clock Architecture ====
 +
 +The clock architecture of the CN0577 is designed with careful consideration to ensure low jitter and low phase noise.
 +
 +An on-board 120 MHz voltage controlled crystal oscillator (VCXO) is used to provide the clock for the CN0577 board and the FPGA. It is further named as ''reference clock''. This clock is gated and fed back to the device as the ''sampling clock'', on which the data was sampled.
 +
 +The DMA runs on the ZynqPS clock FCLK_CLK0 which has a frequency of 100MHz.
  
 ==== Digital Interface ==== ==== Digital Interface ====
  
-==== Analog Input ====+The digital interface consists of the following signals: 
 +  * ''ref_clk_*'' - LVDS clock input, used as reference clock for the system, after it is converted to single-ended signal by ad_data_clk module 
 +  * ''clk_*'' - LVDS clock coming from the FPGA, that serially shifts out the conversion result 
 +  * ''dco_*'' - LVDS clock input 
 +  * ''da_*'' - serial LVDS data input 
 +  * ''db_*'' - serial LVDS data input 
 +  * ''cnv_*'' - conversion start LVDS; a rising edge starts the conversion cycle 
 +  * ''cnv_en'' - signal that is used as CLR_N for the retiming flop from inside the CN0577 board 
 +  * ''pd_cntrl'' - exposed on GPIO 33 
 +  * ''testpat_cntrl'' - exposed on GPIO 32 
 +  * ''twolanes_cntrl'' - hardcoded to 1 to always be used in two-lane mode
  
-==== Power ==== 
  
 +==== ADC Timing Characteristics ====
 +
 +The timing considerations specified in the datasheet of the LTC2387-18 were taken in consideration, and are implemented in the constraints file of the project.
 +
 +What must be noted, is that the ''cnv_en'' signal must be constrained in order to meet timing requirements for tCYC, tCONV, based on tFIRSTCLK and tLASTCLK. ''cnv_en'' being a CLR_N of the retiming flop, forces us to simulate the clock of the retiming flop.
 +
 +In other words, a virtual clock is created, being a shadow of ''ref_clk_*'' (LVDS_CLK in schematic), and because it comes from the output of the **local oscillator**, it needs to be shifted with the propagation delay that is given from passing the **level translator**. Thus, it is shifted with 0.225ns compared to the ref_clk_* signal.
  
-</WRAP> 
  
 ==== Connector and Jumper Configurations ==== ==== Connector and Jumper Configurations ====
 +
 Depending on what configuration of pins is chosen on the jumpers P1, P2 and P3, the device can act in different modes, as described below. Depending on what configuration of pins is chosen on the jumpers P1, P2 and P3, the device can act in different modes, as described below.
-<note>+<note important>
 The PD_N and TESTPAT jumpers must be disconnected because the signals are tied to GPIOs! The PD_N and TESTPAT jumpers must be disconnected because the signals are tied to GPIOs!
 By default, TWOLANES is set to 1 in HDL code! By default, TWOLANES is set to 1 in HDL code!
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 //Of course, the PD jumper overrides the PD signal from the FPGA. It is controlled by a one-bit-adc-dac, in software.// //Of course, the PD jumper overrides the PD signal from the FPGA. It is controlled by a one-bit-adc-dac, in software.//
  
-  * P1 - configures PD_N (powerdown signal that is active on 0) +  * P1 - configures PD_N 
-    * Shorting pins 1 and 2 -> PD_N = 1 (inactive), meaning the device is not powered down +    * Shorting pins 1 and 2 -> PD_N = 1, device is not powered down 
-    * Shorting pins 2 and 3 -> PD_N = 0 (active), meaning the device is powered down+    * Shorting pins 2 and 3 -> PD_N = 0, device is powered down
   * P2 - configures TESTPAT   * P2 - configures TESTPAT
-    * Shorting pins 1 and 2 -> TESTPAT = 1, meaning that the pattern testing is active +    * Shorting pins 1 and 2 -> TESTPAT = 1, pattern testing is active 
-    * Shorting pins 2 and 3 -> TESTPAT = 0, meaning that the pattern testing is inactive+    * Shorting pins 2 and 3 -> TESTPAT = 0, pattern testing is inactive
   * P3 - configures TWOLANES parameter   * P3 - configures TWOLANES parameter
-    * Shorting pins 1 and 2 -> TWOLANES = 1 (meaning it is active in TWO LANES mode) +    * Shorting pins 1 and 2 -> TWOLANES = 1 (TWO LANES mode) 
-    * Shorting pins 2 and 3 -> TWOLANES = 0 (meaning it is active in ONE LANE mode)+    * Shorting pins 2 and 3 -> TWOLANES = 0 (ONE LANE mode)
  
-==== FMC Connector ==== 
 The FMC connector connects to the LPC connector of the carrier board. The FMC connector connects to the LPC connector of the carrier board.
  
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 ===== Software ===== ===== Software =====
  
-==== SD card setup (point to Kuiper wiki page) ==== +The software parts for this IP core can be found at:  
- +  * [[repo>linux/tree/master/drivers/iio/adc/ltc2387.c|CN0577 Linux Kernel driver]]  
-==== IIO_Info ==== +  * [[repo>linux/tree/master/arch/arm/boot/dts/zynq-zed-adv7511-cn0577.dts|CN0577 Devicetree]]
- +
-==== IIO_Oscilloscope ====+
  
  
 ===== Resources ===== ===== Resources =====
  
-  * HDL reference design: [[https://github.com/analogdevicesinc/hdl/tree/master/projects/cn0577|CN0577 HDL project on GitHub]] +  * HDL reference design: [[repo>hdl/tree/master/projects/cn0577|CN0577 HDL project on GitHub]] which uses [[:resources:fpga:docs:axi_ltc2387|AXI_LTC2387]] IP core 
-  * Linux sources: [[|CN0577 devicetree]] and [[|CN0577 Linux Kernel driver]]+  * Wiki page for [[:resources:fpga:docs:axi_ltc2387|AXI_LTC2387]]
   * Schematic: [[ |CN0577 schematic]]   * Schematic: [[ |CN0577 schematic]]
 +  * [[:resources:fpga:docs:arch|HDL Architecture]]
resources/eval/user-guides/circuits-from-the-lab/cn0577/hdl.1660659749.txt.gz · Last modified: 16 Aug 2022 16:22 by Iulia Moldovan

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