This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
resources:eval:user-guides:circuits-from-the-lab:cn0577:hdl [22 Sep 2022 19:07] – Correct explanations Iulia Moldovan | resources:eval:user-guides:circuits-from-the-lab:cn0577:hdl [22 Feb 2023 12:54] (current) – Add Circuit Note page Iulia Moldovan | ||
---|---|---|---|
Line 9: | Line 9: | ||
In order to support high speed operations while minimizing the number of data lines, a serial LVDS digital interface is used. It has a one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application, | In order to support high speed operations while minimizing the number of data lines, a serial LVDS digital interface is used. It has a one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application, | ||
+ | More details about ADI reference designs architecture [[: | ||
===== Evaluation board ===== | ===== Evaluation board ===== | ||
- | * [[ |CN0577 Circuit Note Page]] | + | * [[adi> |
* [[adi> | * [[adi> | ||
Line 21: | Line 22: | ||
===== HDL Design Description ===== | ===== HDL Design Description ===== | ||
<note important> | <note important> | ||
+ | |||
+ | <note important> | ||
The PD and TESTPAT parameters are tied to GPIOs (33 and 32 respectively) so they can be configured by the software. | The PD and TESTPAT parameters are tied to GPIOs (33 and 32 respectively) so they can be configured by the software. | ||
Line 36: | Line 39: | ||
By default, it is set to 1 [[repo> | By default, it is set to 1 [[repo> | ||
+ | |||
+ | === PL interrupts === | ||
+ | |||
+ | When developing the Linux software parts for an HDL project, the interrupts number to the PS have a different number in the software side. | ||
+ | More details [[: | ||
+ | |||
+ | ^Interr. name ^HDL interr. ^Linux Zynq ^Actual Zynq ^ | ||
+ | | axi_ltc2387_dma | ||
+ | |||
+ | === GPIO signals === | ||
+ | |||
+ | PS7 EMIO offset = 54 | ||
+ | |||
+ | ^GPIO HDL name ^GPIO nb. ^HDL GPIO nb.^ | ||
+ | | pd_cntrl | 87 | 33 | | ||
+ | | testpat_cntrl | 86 | 32 | | ||
Line 90: | Line 109: | ||
Depending on what configuration of pins is chosen on the jumpers P1, P2 and P3, the device can act in different modes, as described below. | Depending on what configuration of pins is chosen on the jumpers P1, P2 and P3, the device can act in different modes, as described below. | ||
- | < | + | < |
The PD_N and TESTPAT jumpers must be disconnected because the signals are tied to GPIOs! | The PD_N and TESTPAT jumpers must be disconnected because the signals are tied to GPIOs! | ||
By default, TWOLANES is set to 1 in HDL code! | By default, TWOLANES is set to 1 in HDL code! | ||
Line 105: | Line 124: | ||
* Shorting pins 1 and 2 -> TWOLANES = 1 (TWO LANES mode) | * Shorting pins 1 and 2 -> TWOLANES = 1 (TWO LANES mode) | ||
* Shorting pins 2 and 3 -> TWOLANES = 0 (ONE LANE mode) | * Shorting pins 2 and 3 -> TWOLANES = 0 (ONE LANE mode) | ||
- | |||
- | ==== FMC Connector ==== | ||
The FMC connector connects to the LPC connector of the carrier board. | The FMC connector connects to the LPC connector of the carrier board. | ||
Line 123: | Line 140: | ||
* Wiki page for [[: | * Wiki page for [[: | ||
* Schematic: [[ |CN0577 schematic]] | * Schematic: [[ |CN0577 schematic]] | ||
+ | * [[: |