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resources:eval:user-guides:circuits-from-the-lab:cn0568 [29 Jun 2021 14:24] – Kieran Barrett | resources:eval:user-guides:circuits-from-the-lab:cn0568 [15 Nov 2021 16:35] (current) – old revision restored (15 Nov 2021 16:33) Kieran Barrett | ||
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===== Hardware ===== | ===== Hardware ===== | ||
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{{: | {{: | ||
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===== Software Installation ===== | ===== Software Installation ===== | ||
+ | 1. Download the software folder from the CN-568 product page. | ||
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+ | 2. Double click on the ' | ||
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+ | 3. Follow the installation windows that appear, to install the software in the default location as shown in the screenshots below. | ||
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+ | 4. After the CN0568 software has installed, an installation window for the SDP drivers will appear. If the SDP drivers have not previously been installed on the machine, proceed with this installation step. | ||
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+ | {{: | ||
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+ | 5. Load the custom firmware to the SDP-K1 board by dragging and dropping the ' | ||
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===== Software Interface ===== | ===== Software Interface ===== | ||
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The interface used to control the circuit is described in this section. The are 3 regions of the software interface panel as shown below. | The interface used to control the circuit is described in this section. The are 3 regions of the software interface panel as shown below. | ||
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== Divider and Doubler == | == Divider and Doubler == | ||
- | These can be used to change the PFD frequency accordingly on the ADF41513. | + | These can be used to change the PFD frequency accordingly on the [[adi> |
=== Frequency Control === | === Frequency Control === | ||
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=== Phase Control === | === Phase Control === | ||
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The phase of an output signal can be incremented by specifying the value in the Phase Value field. The phase is calculated and can be updated by pressing the Increment Phase button. | The phase of an output signal can be incremented by specifying the value in the Phase Value field. The phase is calculated and can be updated by pressing the Increment Phase button. | ||
Phase resync is enabled by default within the initialization sequence. To set the phase resync time, set the CLK1 and CLK2 multipliers accordingly. Note: the phase resync time must be greater than the worst case lock time. | Phase resync is enabled by default within the initialization sequence. To set the phase resync time, set the CLK1 and CLK2 multipliers accordingly. Note: the phase resync time must be greater than the worst case lock time. | ||
==== Hop Function Tab==== | ==== Hop Function Tab==== | ||
- | A hop function | + | |
- | // Input Hop function image. | + | A frequency |
+ | {{: | ||
=== Dual Board Control === | === Dual Board Control === | ||
+ | A dual board configuration can be used when two boards of the same VCO variant are connected via a stacked connection from the Arduino style header. This first must be selected in the Board Configuration section prior to a software connection being established to the board. When using the dual board configuration, | ||
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+ | To use the dual board configuration, | ||
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=== Other Functions === | === Other Functions === | ||
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+ | Some of the basic register controls of the [[adi> | ||
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===== Evaluation Setup ===== | ===== Evaluation Setup ===== | ||
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{{: | {{: | ||
===== Required Equipment ===== | ===== Required Equipment ===== | ||
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* Spectrum Analyzer | * Spectrum Analyzer | ||
* 1 x 50 Ω, RF / Microwave cable with 2.92mm connectors | * 1 x 50 Ω, RF / Microwave cable with 2.92mm connectors | ||
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6. In the spectrum analyzer instrument, set up a phase noise measurement. | 6. In the spectrum analyzer instrument, set up a phase noise measurement. | ||
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7. Table 1. below lists the test frequencies for each part variant. On the evaluation software, in the ‘VCO Out’ box, input the first frequency for the variant used and press ‘Update Frequency’ button. | 7. Table 1. below lists the test frequencies for each part variant. On the evaluation software, in the ‘VCO Out’ box, input the first frequency for the variant used and press ‘Update Frequency’ button. | ||
{{: | {{: | ||
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8. Wait until the instrument locks to the output frequency and displays the phase noise profile on screen. Note the phase noise at offsets of 100kHz, 1MHz and 10MHz. | 8. Wait until the instrument locks to the output frequency and displays the phase noise profile on screen. Note the phase noise at offsets of 100kHz, 1MHz and 10MHz. | ||
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9. Table 2. shows the limits of the maximum phase noise at a particular offset frequency for each variant. Boards with phase noise higher than these limits are deemed to be failures. | 9. Table 2. shows the limits of the maximum phase noise at a particular offset frequency for each variant. Boards with phase noise higher than these limits are deemed to be failures. | ||
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10. Repeat steps 7-9 for each test frequency in Table 1. for the board variant being tested. | 10. Repeat steps 7-9 for each test frequency in Table 1. for the board variant being tested. | ||
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- | ===== Schematic, PCB Layout, Bill of Materials ===== | ||
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- | [[adi> | ||
- | * Schematics | ||
- | * PCB Layout | ||
- | * Bill of Materials | ||
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- | ===== Additional Information and Useful Links ===== | ||
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- | * [[https:// | ||
- | * [[ADI> | ||
- | * [[ADI> | ||
- | * [[ADI> | ||
- | * [[ADI> | ||
- | * [[ADI> | ||
- | * [[ADI> | ||
- | * [[ADI> | ||
- | * [[ADI> | ||
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- | ====== Reference Demos & Software ====== | ||
- | * [[resources: | ||
- | * [[resources: | ||
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- | // End of Document // |