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CN0568:Ultra-fast switching, High Performance PLL and Quadband VCO frequency synthesizer with phase resync

CN0568 This circuit demonstrates the performance of ADI's quadband VCOs with the ADF41513 PLL device. The circuit design provides a complete frequency synthesizer solution including supply regulators, and control circuitry.

The key components used in this circuit are as follows:

Hardware

Software Installation

Software Interface

Main Controls

Reference Configuration

Frequency Control

Phase Control

Hop Function

Dual Board Control

Other Functions

Evaluation Setup

Required Equipment

  • Spectrum Analyzer
  • 1 x 50 Ω, RF / Microwave cable with 2.92mm connectors
  • 2 x BNC to SMA adapter
  • 2 x Dual banana plug to BNC socket
  • 2 x 50 Ω SMA DC cables

Procedure

1. Download and install the CN0568 board software from the product page on analog.com. 2. Set up the evaluation board as shown in the setup image above with:

  • +5v connected to J1 and +25v connected V+SMA of the DC power supply (ensuring supply outputs are switched off). *
  • Set current limit of +5v supply to 200mA and set current limit of +25v supply to 20mA.
  • Evaluation board mounted to the Arduino header of the SDP-K1.
  • USB cable connected to the host PC from the SDP-K1 Eval board.
  • 50 Ω 2.92mm RF cable connected from RFOUT of the evaluation board to RFIN of the FSW/FSWP.

3. Open the software and select the relevant part/board variant.

4. Turn on the 5v power supply. Then turn on the 25v power supply.

5. Press ‘Write Initialization Sequence’ button to initialize the part.

  • The current drawn on the +5v supply should be between 150-180mA.
  • The current drawn on the +25v supply should be approximately 4mA.

6. In the spectrum analyzer instrument, set up a phase noise measurement. 7. Table 1. below lists the test frequencies for each part variant. On the evaluation software, in the ‘VCO Out’ box, input the first frequency for the variant used and press ‘Update Frequency’ button. 8. Wait until the instrument locks to the output frequency and displays the phase noise profile on screen. Note the phase noise at offsets of 100kHz, 1MHz and 10MHz. 9. Table 2. shows the limits of the maximum phase noise at a particular offset frequency for each variant. Boards with phase noise higher than these limits are deemed to be failures. 10. Repeat steps 7-9 for each test frequency in Table 1. for the board variant being tested.

Schematic, PCB Layout, Bill of Materials

EVAL-CN0xxx-ARDZ Design & Integration Files

  • Schematics
  • PCB Layout
  • Bill of Materials

Reference Demos & Software

resources/eval/user-guides/circuits-from-the-lab/cn0568.1624519252.txt.gz · Last modified: 24 Jun 2021 09:20 by Kieran Barrett