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--- resources:eval:user-guides:circuits-from-the-lab:cn0560 [07 Jun 2022 04:41] – [Hardware Connection] Rainier Rosario
+++ resources:eval:user-guides:circuits-from-the-lab:cn0560 [14 Jun 2022 01:24] (current) – [Navigating the Evaluation Software] Rainier Rosario
@@ Line 2: / Line 2: @@
 ====== EVAL-CN0560-FMCZ User Guide ======
-[[ADI>CN0560]] The EVAL-CN0560-FMCZ evaluation board (Figure 1) features high-accuracy measurement of three current ranges using a combination of shunt resistors and on-board amplifiers driving the 18-bit, 15MSPS [[adi>ADAQ23878]] precision µModule® data acquisition solution. The evaluation board demonstrates the performance of the [[adi>ADAQ23878]]  µModules and is a versatile tool for a variety of applications.
+[[ADI>CN0560]] The EVAL-CN0560-FMCZ evaluation board (Figure 1) features high-accuracy measurement of three current ranges using a combination of shunt resistors and on-board amplifiers driving the 18-bit, 15MSPS [[adi>ADAQ23878]] precision µModule® data acquisition solution.
 The [[adi>ADAQ23878]] µModule combines multiple common signal processing and conditioning blocks into a single device that includes a low noise, fully differential analog-to-digital converter (ADC) driver, a stable reference buffer, a high resolution, 18-bit, 15 MSPS successive approximation register (SAR) ADC, and the critical passive components necessary for optimum performance. A full description of this product is available in the [[adi>ADAQ23878]]  data sheet, which must be consulted when using the evaluation board.
@@ Line 23: / Line 23: @@
   * Current Source (ex. Keithley 2400)
   * Standard USB A to USB mini-B
-  * Voltage Supply (ex. Keithley E3631A)
+  * DC Bench top Power Supply (ex. Keithley E3631A)
 ==== Software Required ====
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 ==== Hardware Connection ====
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+**Figure 2 10uA Setup Connection**
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-**Figure 2 Simplified Evaluation Setup for 10uA Range**
+{{ :resources:eval:user-guides:circuits-from-the-lab:10ua_test_setup.jpg?600 |}}
-{{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:10ua_setup.jpg?600 |}}
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-**Figure 3 Simplified Evaluation Setup for 10mA Range**
+**Figure 3 10mA Setup Connection**
-{{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:10ma_setup.jpg?600 |}}
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+{{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:10ma_test_setup.jpg?600 |}}
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-**Figure 4 Simplified Evaluation Setup for 10A Range**
-{{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:10a_setup.jpg?600 |}}
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+**Figure 4 10A Setup Connection**
+\\
+{{ :resources:eval:user-guides:circuits-from-the-lab:10a_test_setup.jpg?600 |}}
+\\
+\\
 ==LINK CONFIGURATION OPTIONS==
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-**SIMPLFIED BLOCK DIAGRAM**
+**FIGURE 5 SIMPLFIED BLOCK DIAGRAM**
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 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:block_diagram2.jpg?600 |}}
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-The figure above shows the simplified evaluation board block diagram of the Eval-CN0560-FMC. The board consists of one µModule (U1,  [[adi>ADAQ23878]]), a choice of a 4.096 V reference (U5, [[adi>LTC6655]]) or 2.048V reference (U3, [[adi>ADR4520]]), on-board power supplies to derive the necessary supply rails using the two [[adi>LTM8049]] (U6 and U2), the [[adi>ADP7118]] (U4), the [[adi>ADP7183]] (U7), the [[adi>LT3023]] (U8), [[adi>LT3032]] (U16), and a [[adi>AD9513]] 800 MHz clock distribution IC (U13). Right after the [[adi>ADG5209]] (U20) multiplexer for current range selection, the user also has an option to use the two frontend amplifier options [[adi>ADA4898-1]] amplifiers (U9 and U10) and the [[adi>LT5400]] (RN1) or a single [[adi>AD8421]] when evaluating the EVAL-CN0560-FMCZ .
+Figure 5 shows the simplified evaluation board block diagram of the Eval-CN0560-FMC. The board consists of one µModule (U1,  [[adi>ADAQ23878]]), a choice of a 4.096 V reference (U5, [[adi>LTC6655]]) or 2.048V reference (U3, [[adi>ADR4520]]), on-board power supplies to derive the necessary supply rails using the two [[adi>LTM8049]] (U6 and U2), the [[adi>ADP7118]] (U4), the [[adi>ADP7183]] (U7), the [[adi>LT3023]] (U8), [[adi>LT3032]] (U16), and a [[adi>AD9513]] 800 MHz clock distribution IC (U13). Right after the [[adi>ADG5209]] (U20) multiplexer for current range selection, the user also has an option to use the two frontend amplifier options [[adi>ADA4898-1]] amplifiers (U9 and U10) and the [[adi>LT5400]] (RN1) or a single [[adi>AD8421]] when evaluating the EVAL-CN0560-FMCZ .
 **SDP-H1 CONTROLLER BOARD**
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 **POWER SUPPLIES**
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-The CN-0560 board requires the SDP-H1 controller board for high accuracy data capture. All the power rails on board can be generated from a 3.3 V rail coming from the SDP-H1 board or an optional external 3.3V bench supply using the JP9 solder link if desired (see Table 1).  The simplified power tree used on the CN-0560 board is shown in the figure below. The two [[adi>LTM8049]] dual SEPIC or inverting μModule DC/DC converters generate +7V, - 2.5V, +15.5V, and -15.5V rails from a 3.3V rail. The [[adi>LT3023]] dual low noise, micropower LDO generates +5V and +6.5V rails from a +7V, while the [[adi>ADP7183]] ultralow noise LDO generates -2V rail from -2.5V.
+The CN-0560 board requires the SDP-H1 controller board for high accuracy data capture. All the power rails on board can be generated from a 3.3 V rail coming from the SDP-H1 board or an optional external 3.3V bench supply using the JP9 solder link if desired (see Table 1).  The simplified power tree used on the CN-0560 board is shown in the Figure 6.
+\\
+The two [[adi>LTM8049]] dual SEPIC or inverting μModule DC/DC converters generate +7V, - 2.5V, +15.5V, and -15.5V rails from a 3.3V rail. The [[adi>LT3023]] dual low noise, micropower LDO generates +5V and +6.5V rails from a +7V, while the [[adi>ADP7183]] ultralow noise LDO generates -2V rail from -2.5V.
+\\
 The +6.5V and -2V rails are used for the integrated FDA of [[adi>ADAQ23878]], while the +5V rail is used for the LTC6655 to produce a 4.096V reference. Two rails of +15.5V and -15.5V from the second [[adi>LTM8049]] are fed in to the [[adi>LT3032]] dual  LDO to produce +15V and -15V voltage rails for the [[adi>ADA4898-1]] and the [[adi>ADG5209]]. The [[adi>ADP7118]] low noise LDO generates a +2.5V rail for the [[adi>ADR4520]] to produce a 2.048V reference.
+\\
 Each supply rail has necessary decoupling capacitors placed closed to the device. A single ground plane is used on this board to minimize the effect of high frequency noise interference.
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+**FIGURE 6 POWER TREE**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:cn0560:power_tree.jpg?600 |{{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:cn0560:power_tree.jpg?600 |}}
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-The actual selection of the measurement range is controlled by the configuration of the [[adi>ADG5209]] multiplexer. The multiplexer configuration is controlled by the position of the shunt connectors on the headers P13, P7, P14, and P8. The headers P13 and P14 are provisions for user to control the selected current range by software or to manually control it by headers P7 and P8. Refer to the figures below for the link header configuration for current range selection and corresponding hardware connection figures for different input ranges
+The actual selection of the measurement range is controlled by the configuration of the [[adi>ADG5209]] multiplexer. The multiplexer configuration is controlled by the position of the shunt connectors on the headers P13, P7, P14, and P8. The headers P13 and P14 are provisions for user to control the selected current range by software or to manually control it by headers P7 and P8. Refer to the Figure 7 to Figure 11 for the link header configuration for current range selection and the corresponding hardware connection on Figure 2 to Figure 4 for different input ranges.
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-**Software Controlled**
+**Figure 7 Software Controlled**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:range_sw.jpg?300 |}}
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-**10uA Input Range**
+**Figure 8 10uA Input Range**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:range_10ua.jpg?300 |}}
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-**10mA Input Range**
+**Figure 9 10mA Input Range**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:range_10ma.jpg?300 |}}
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-**10A Input Range**
+**Figure 10 10A Input Range**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:range_10a.jpg?300 |}}
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-**Grounded Inputs**
+**Figure 11 Grounded Inputs**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:range_gnd_in.jpg?300 |}}
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-Following the multiplexer are two [[adi>ADA4898-1]] High Voltage, Low Noise, Low Distortion, Unity Gain Stable, High Speed Operational Amplifiers. The two unity gain op amps have [[adi>LT5400]] Quad Matched Resistor Network for a precise ratiometric stability for high accuracy difference amplifier and for a guaranteed CMRR performance that is 2x better than independently matched resistors. If the two [[adi>ADA4898-1]] is not preferred, an optional [[adi>AD84211]] 3 nV /√Hz, Low Power Instrumentation Amplifier is provided in the reference circuit. The In-Amp can be used by disconnecting the two unity gain op amps by modifying the connections of JP1, JP2, JP7, and JP8 to their alternate signal paths.
+Following the multiplexer are two [[adi>ADA4898-1]] High Voltage, Low Noise, Low Distortion, Unity Gain Stable, High Speed Operational Amplifiers. The two unity gain op amps use the [[adi>LT5400]] Quad Matched Resistor Network for a precision ratiometric stability for CMRR better than independently matched resisitors. If the two [[adi>ADA4898-1]] are not preferred, an optional [[adi>AD8421]] 3 nV /√Hz, Low Power Instrumentation Amplifier is provided in the reference circuit. The In-Amp can be used by disconnecting the two unity gain op amps by modifying the connections of JP1, JP2, JP7, and JP8 to their alternate signal paths.
-The [[adi>ADAQ23878]] gain for its frontend high speed FDA are configured by how the signal is applied on its input pins. For the CN-0560 Reference Design Board, the gain can be configured using the header connections on P4 and P6. The gain settings configuration using header connections are described in the figures below.
+The gain for the  [[adi>ADAQ23878]] FDA is configured by how the signal is applied on its input pins. For the CN-0560 Reference Design Board, the gain can be configured using the header connections on P4 and P6. The gain settings configuration using header connections are described in Figure 12 to Figure 15.
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-**Gain = 0.37**
+**Figure 12 Gain = 0.37**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:gain_0.37.jpg?300 |}}
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-**Gain = 0.73**
+**Figure 13 Gain = 0.73**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:gain_0.73.jpg?300 |}}
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-**Gain = 1.38**
+**Figure 14 Gain = 1.38**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:gain_1.38.jpg?300 |}}
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-**Gain = 2.25**
+**Figure 15 Gain = 2.25**
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:gain_2.25.jpg?300 |}}
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-To evaluate dynamic performance, a fast Fourier transform (FFT), integral nonlinearity (INL), differential nonlinearity (DNL), or time domain (waveform, histogram) test can be performed by applying a very low distortion ac source (see figures for the Analysis Window for examples of dynamic performance results). For low input frequency testing below 100 kHz, it is recommended to use a low noise, audio precision signal source (such as the SYS-2700 series) with the outputs set to balanced floating. A different precision signal source can be used alternatively with additional band-pass filtering. The filter bandwidth depends on input bandwidth of interest.
+To evaluate dynamic performance, fast Fourier transform (FFT), integral nonlinearity (INL), differential nonlinearity (DNL), or time domain (waveform, histogram) test can be performed by applying a very low distortion ac source (see figures for the Analysis Window for examples of dynamic performance results). For low input frequency testing below 100 kHz, it is recommended to use a low noise, audio precision signal source (such as the SYS-2700 series) with the outputs set to balanced floating. A different precision signal source can be used alternatively with additional band-pass filtering. The filter bandwidth depends on input bandwidth of interest.
+\\
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 To measure Dynamic performance of the CN0560, follow the steps below:
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   - Remove the 5kΩ Rshunt (R29) on the 10uA input path
-  - Connect the Signal Source (AP2722) to the CN0560 board and SDP-H1 as shown on Figure.
+  - Connect the Signal Source (AP2722) to the CN0560 board and SDP-H1 as shown on Figure 16.
   - Set the output of the AP2722 to 50mV pk-pk.
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-{{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:ac_meas_setup.png?600 |}}
+**FIGURE 16 DYNAMIC PERFORMANCE SETUP**
+\\
+{{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:ap2722_dr_setup.jpg?600 |}}
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 ==== Navigating the Evaluation Software ====
-Upon opening ACE, the ADAQ23878 Board should be detected.
+Upon opening ACE, the ADAQ23878 Board should be detected as shown in Figure 17.
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-**Main Window**
+**Figure 17 Main Window**
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 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:ace_main_window.jpg?600 |}}
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-From the Main Window, double click on the ADAQ23878 board to open the Board View
+From the Main Window, double click on the ADAQ23878 board to open the Board View as shown in Figure 18.
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-**Board View**
+**Figure 18 Board View**
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 The Board View shows an overview of the components on the evaluation board.
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 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:board_view.jpg?600 |}}
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-From Board View, double click on the ADAQ23878 icon to open the Chip View.
+From Board View, double click on the ADAQ23878 icon to open the Chip View as shown in Figure 19.
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-**Chip View**
+**Figure 19 Chip View**
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 The Chip View shows an overview of the internal block diagram of the ADAQ23878 uModule.
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-**Analysis Window**
+**Figure 20 Analysis Window**
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 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:analysis.jpg?600 |}}
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   * Capture Panel
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-Throughputs. The default throughput (sampling frequency) is 15MSPS. The user can adjust the throughput to a minimum of 20 kSPS. If the user enters a value larger than the ability of the existing device, the software reverts to the maximum throughput. Refer to the ADAQ23878/ADAQ23876 data sheet to determine the maximum sampling frequency.
+Throughput. The default throughput (sampling frequency) is 15MSPS. The user can adjust throughput to a minimum of 20 kSPS. If the user enters a value larger than ability of the existing device, the software reverts to the maximum throughput. Refer to the ADAQ23878/ADAQ23876 data sheet to determine the maximum sampling frequency.
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 The Number of samples dropdown list in the Capture Settings section allows the user to select the number of samples per channel per capture. The maximum number of samples the software can support is 1048576.
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 Device Setting Digital Input that Enables Two-Lane Output Mode and One lane mode. When TWOLANES is connected high (two-lane output mode), the [[adi>ADAQ23878]]/[[adi>ADAQ23876]] outputs 2 bits at a time on DA−/DA+ and DB−/DB+. When TWOLANES is low (one-lane output mode), the [[adi>ADAQ23875]] outputs 1 bit at a time on DA−/DA+, and DB−/DB+ are disabled. Logic levels are determined by VIO. Refer to Table 1 P1 to configure the board to different mode.
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-Software Oversampling Ratio box as shown in Figure 13 sets the oversampling ratio applied to the captured data. After this control is set to any value other than "Off", the software sums up the consecutive conversion results together to increase the effective resolution. The number of conversions summed together is set by the Oversampling Ratio box. Oversampling by a factor of four provides one additional bit of resolution, or a 6 dB increase in dynamic range, or in other words, ΔDR = 10 × log10(OSR) in dB.
+Software Oversampling Ratio box as shown in Figure 13 sets the oversampling ratio applied to the captured data. Oversampling refers to sampling faster than twice the signal bandwidth required for Nyquist criterion.  After this control is set to any value other than "Off", the software sums up the consecutive conversion results together to increase the effective resolution. The number of conversions summed together is set by the Oversampling Ratio box. Oversampling by a factor of four provides one additional bit of resolution, or a 6 dB increase in dynamic range, or in other words, ΔDR = 10 × log10(OSR) in dB.
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 The General Settings section allows the user to set up the preferred configuration of the FFT analysis. This configuration sets how many tones are analyzed and if the fundamental is set manually.
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-The Windowing section allows the user to set up the preferred windowing type to use in the FFT analysis and the number of harmonic bins and fundamental bins that must be included in the analysis.
+The Windowing section allows the user to set up preferred windowing type to use in the FFT analysis and the number of harmonic bins and fundamental bins that must be included in the analysis.
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-The Single Tone Analysis and the Two-Tone Analysis sections sets up the fundamental frequencies included in the FFT analysis. When one frequency is analyzed, use the Singe Tone Analysis section. When two frequencies are analyzed, use the Two-Tone Analysis section.
+The Single Tone Analysis and the Two-Tone Analysis sections set up the fundamental frequencies included in the FFT analysis. When one frequency is analyzed, use the Singe Tone Analysis section. When two frequencies are analyzed, use the Two-Tone Analysis section.
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-  * Waveform Tab
+  * Figure 21 Waveform Tab
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 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:waveform.jpg?600 |}}
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-  * Histogram Tab
+  * Figure 22 Histogram Tab
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 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:histogram.jpg?600 |}}
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-  * FFT Tab
+  * Figure 23 FFT Tab
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 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:fft.jpg?600 |}}
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 ΔDR = 10 × log10 (OSR) (in dB)
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+Figure 24 Oversampling
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:oversampling.jpg?600 |}}
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   * INL & DNL Tab
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+Figure 25
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:inl.jpg?600 |}}
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+Figure 26
 {{ :resources:eval:user-guides:circuits-from-the-lab:cn0560:dnl.jpg?600 |}}
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 The INL and DNL tab displays linearity analysis. INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
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-In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed.
+In an ideal μModule, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed.
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 To perform a linearity test, apply a sinusoidal signal with 0.5 dB above full scale to the EVAL-CN0560-FMCZ board at the VIN+ and VIN− Subminiature Version A (SMA) inputs. Set the number of hits per code and adjust to the desired accuracy. Using a large number of hits per code results in a significant test time. The figures above display captured data that includes the ±INL and ±DNL positions.

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