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resources:eval:user-guides:adrv9009:reference_hdl [05 Jun 2018 16:59] – Fixed title Adrian Costinaresources:eval:user-guides:adrv9009:reference_hdl [06 Jun 2018 12:26] – Removed PRBS from the DAC path description Adrian Costina
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 ===== Digital Interface ===== ===== Digital Interface =====
  
-The digital interface consists of 4 transmit, 2 receive and 2 observation/sniffer lanes running up to 9.8Gbps. The transceivers then interface to the cores at 128bits@245MHz in the transmit and 64bits@245MHz for the receive channels. The sniffer/observation rates depends on the mode selected. The data is sent or received based on the configuration (programmable) from separate transmit and receive chains.+The digital interface consists of 4 transmit, 2 receive and 2 observation/sniffer lanes running up to 9.8Gbps. The transceivers then interface to the cores at 128bits@245MHz in the transmit and 64bits@245MHz for the receive channels. The sniffer/observation rates depend on the mode selected. The data is sent or received based on the configuration (programmable) from separate transmit and receive chains.
  
 ===== DAC Interface ===== ===== DAC Interface =====
  
-The DAC data may be sourced from an internal data generator (DDS, pattern or PRBS) or from the external DDR via DMA. The internal DDS phase and frequency are programmable.+The DAC data may be sourced from an internal data generator (DDS or pattern) or from the external DDR via DMA. The internal DDS phase and frequency are programmable. DAC UNPACK IP (util_upack) allows transfering data from the DMA to a reduced number of channels, at a higher rate.
  
 ===== ADC Interface ===== ===== ADC Interface =====
  
-The ADC data is sent to the DDR via DMA.+The ADC data is sent to the DDR via DMA. The ADC PACK IP (util_cpack) allows capturing only part of the channels.
  
 ===== Control and SPI ===== ===== Control and SPI =====
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 {{page>resources/fpga/docs/hdl/downloads_insert_dev_adrv9009#adrv9009}} {{page>resources/fpga/docs/hdl/downloads_insert_dev_adrv9009#adrv9009}}
 {{page>resources/fpga/docs/hdl/downloads_insert#help_support}} {{page>resources/fpga/docs/hdl/downloads_insert#help_support}}
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resources/eval/user-guides/adrv9009/reference_hdl.txt · Last modified: 05 Oct 2022 11:21 by Stanca-Florina Pop

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