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This version (07 Aug 2018 11:54) was approved by Adrian Costina.The Previously approved version (06 Jun 2018 12:26) is available.Diff

ADRV9009 HDL Reference Design

Functional Overview

The HDL reference design is an embedded system built around a processor core either ARM, NIOS-II or Microblaze. A functional block diagram of the system is shown below. The device digital interface is handled by the transceiver IP followed by the JESD204B and device specific cores. The JESD204B lanes are shared among the 4 transmit, 2 receive and 2 observation/sniffer receive data paths by the same set of transceivers within the IP. The cores are programmable through an AXI-lite interface. The delineated data is then passed on to independent DMA cores for the transmit, receive and observation/sniffer paths.

Digital Interface

The digital interface consists of 4 transmit, 2 receive and 2 observation/sniffer lanes running up to 9.8Gbps. The transceivers then interface to the cores at 128bits@245MHz in the transmit and 64bits@245MHz for the receive channels. The sniffer/observation rates depend on the mode selected. The data is sent or received based on the configuration (programmable) from separate transmit and receive chains.

DAC Interface

The DAC data may be sourced from an internal data generator (DDS or pattern) or from the external DDR via DMA. The internal DDS phase and frequency are programmable. DAC UNPACK IP (util_upack) allows transfering data from the DMA to a reduced number of channels, at a higher rate.

ADC Interface

The ADC data is sent to the DDR via DMA. The ADC PACK IP (util_cpack) allows capturing only part of the channels.

Control and SPI

The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.

Download

The HDL repository, list of supported carriers and the list of required IP cores can be found here:

Projects list and dependencies for master

AD40XXFMC

AD469XFMC

AD5758SDZ

AD5766SDZ

AD6676EVB

AD7134FMC

AD738xFMC

AD7405FMC

AD7616SDZ

AD77681EVB

AD7768EVB

AD9081FMCAEBZ

AD9082FMCAEBZ

AD9083EVB

AD9208DUALEBZ

AD9265FMC

AD9434FMC

AD9467FMC

AD9656FMC

AD9739AFMC

ADFMCLIDAR1EBZ

ADAQ7980SDZ

ADRV9001

ADRV9008/9

ADRV9371

ADV7511OnBoard

ADV7513OnBoard

Hardware Project Carriers Resource Utilization Library Cores
ADV7513 adv7513 de10nano NA axi_dmac
axi_hdmi_tx
util_axis_fifo

ARRadio

Hardware Project Carriers Resource Utilization Library Cores
ARRadio arradio c5soc NA axi_ad9361
axi_dmac
axi_sysid
sysid_rom
util_axis_fifo
util_cdc
util_cpack2
util_rfifo
util_upack2

CN0363

CN0501

Hardware Project Carriers Resource Utilization Library Cores
CN0501 cn0501 coraz7s cn0501_coraz7s axi_dmac
axi_generic_adc
axi_sysid
sysid_rom
util_axis_fifo
util_cdc

CN0506MII

CN0506RGMII

CN0506RMII

CN0540

DACFMCEBZ

FMCDAQ2

FMCDAQ3

FMCADC2/FMCADC3

FMCADC5

FMCJESDADC1

FMCOMMS11

FMCOMMS2/FMCOMMS3/FMCOMMS4

FMCOMMS5

FMCOMMS8

FMCIMAGEONG

Help & Support

13 Feb 2015 18:57 · rejeesh kutty

Help & Support

13 Feb 2015 18:57 · rejeesh kutty
resources/eval/user-guides/adrv9009/reference_hdl.txt · Last modified: 07 Aug 2018 11:54 by Adrian Costina