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| resources:eval:user-guides:adrv9009-zu11eg:syncronization [15 Jun 2021 14:22] – [ADRV9009-ZU11EG Multi-SOM Synchronization] Michael Hennerich | resources:eval:user-guides:adrv9009-zu11eg:syncronization [21 Feb 2024 09:06] (current) – [Reference distribution] Michael Hennerich | ||
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| ===== Clock tree synchronization considerations ===== | ===== Clock tree synchronization considerations ===== | ||
| - | The HMC7044 used throughout the entire clock-tree in this design supports two alternative synchronizations modes and methods. Both modes may have their own benefits and tradeoffs, such as Jitter, Correlated Close in Phase Noise, Timing Requirements, Phase Synchronization reliability over PVT, unwanted | + | The HMC7044 used throughout the entire clock-tree in this design supports two alternative synchronizations modes and methods. Both modes may have their own benefits and tradeoffs, such as: |
| + | * Jitter | ||
| + | * Correlated Close in Phase Noise | ||
| + | * Timing Requirements | ||
| + | * Phase Synchronization reliability over PVT | ||
| + | * Unwanted | ||
| + | * Thermal Drift | ||
| + | * Power Consumption | ||
| + | * etc. | ||
| We recommend planning for and evaluating both options. | We recommend planning for and evaluating both options. | ||
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| ==== Reference distribution ==== | ==== Reference distribution ==== | ||
| + | |||
| + | {{ : | ||
| A lower frequency reference is used between different levels in the clock tree (Inter-stage Frequency). All clock-chips in the hierarchy require its own local VCXO and this reference is used to lock the VCXO using PLL1 to the external reference. Any of the four available reference inputs '' | A lower frequency reference is used between different levels in the clock tree (Inter-stage Frequency). All clock-chips in the hierarchy require its own local VCXO and this reference is used to lock the VCXO using PLL1 to the external reference. Any of the four available reference inputs '' | ||
| Line 14: | Line 25: | ||
| A additional '' | A additional '' | ||
| + | ^ Function ^ File ^ | ||
| + | | dts | [[linux.github> | ||
| + | | dts | [[linux.github> | ||
| + | | dts | [[linux.github> | ||
| + | | dts | [[linux.github> | ||
| + | |||
| + | <note warning> | ||
| + | Depending on the Linux/ | ||
| + | [[repo> | ||
| + | |||
| + | < | ||
| + | arch: arm64: adrv9009-zu11eg: | ||
| + | To match default AD-SYNCHRONA14-EBZ configuration: | ||
| + | |||
| + | CH8 - HMC7044 CLKOUT4 - CMOS | ||
| + | CH10 - HMC7044 CLKOUT5 - LVPECL AC-COUPLED | ||
| + | CH6 - HMC7044 CLKOUT6 - CMOS | ||
| + | CH9 - HMC7044 CLKOUT12 - LVPECL AC-COUPLED | ||
| + | </ | ||
| + | </ | ||
| ==== Clock distribution ==== | ==== Clock distribution ==== | ||
| + | |||
| + | {{ : | ||
| The maximum frequency used in the system is generated by the topmost HMC7044 and then distributed throughout the entire clock tree (Inter-stage Frequency). | The maximum frequency used in the system is generated by the topmost HMC7044 and then distributed throughout the entire clock tree (Inter-stage Frequency). | ||
| Line 20: | Line 53: | ||
| This method is referred as **clock distribution**. All lower level clock-chips receive their input clock via '' | This method is referred as **clock distribution**. All lower level clock-chips receive their input clock via '' | ||
| - | Depending on your [[resources: | + | <note tip>This mode also allows for TRX baseband rates that would be otherwise not possible with the default installed VCXO of 122.880MHz. Let's say someone needs exactly 250.000MSPS. This becomes possible by providing a 500.000MHz or 1000.000MHz external clock.</ |
| + | |||
| + | Depending on your [[resources: | ||
| + | |||
| + | <note important> | ||
| + | * Replace C18, C19, C236, C240 with 0 Ohm resistors | ||
| + | * Replace C289, C290 with 0 Ohm resistors | ||
| + | * Unload 0 Ohm resistors from location R77, R112 and insert to R110, R111 | ||
| + | Rev C.1: | ||
| + | * Replace C289, C290 with 0 Ohm resistors | ||
| + | * Unload 0 Ohm resistors from location R77, R112 and insert to R110, R111 | ||
| + | </ | ||
| - | | C289 | bypass/ | + | ^ Function ^ File ^ |
| - | | C290 | bypass/short | | + | | dts | [[linux.github> |
| - | | R110 | insert/short | | + | | dts | [[linux.github> |
| - | | R111 | insert/short | | + | |
| ===== Hardware setup ===== | ===== Hardware setup ===== | ||
| Line 60: | Line 103: | ||
| ===== Software ===== | ===== Software ===== | ||
| - | * 11/ | + | * [[:resources:tools-software:linux-software:kuiper-linux |Analog Devices Kuiper Linux]] |
| - | * {{ :resources:eval:user-guides:adrv9009-zu11eg:adrv9009_zu11eg_fmcomms8_nov9_2020.zip |ADRV9009-ZU11EG+FMCOMMMS8 Boot Files}} | + | |
| - | * 02/ | + | |
| - | * {{ : | + | |
| - | * {{ : | + | |
| <note tip>The board which connects the external HMC7044 clockchip is refered as **primary** and requires the devicetree (system.dtb) from the primary folder in the archive. Likewise the board without the external clockchip connected is called **secondary**, | <note tip>The board which connects the external HMC7044 clockchip is refered as **primary** and requires the devicetree (system.dtb) from the primary folder in the archive. Likewise the board without the external clockchip connected is called **secondary**, | ||
| Line 73: | Line 112: | ||
| There are two domains of synchronization that are considered in this configuration, | There are two domains of synchronization that are considered in this configuration, | ||
| - | {{ : | + | The System Clocking Tree Diagram is located here: |
| + | {{ : | ||
| During multi-chip synchronization (MCS), which is a feature of the ADRV9009s, all baseband data from the converters is synchronized across transceiver chips. This requires specific sysrefs to be captured at each of the transceiver simultaneously. This will also create deterministic phase differences between transceivers, | During multi-chip synchronization (MCS), which is a feature of the ADRV9009s, all baseband data from the converters is synchronized across transceiver chips. This requires specific sysrefs to be captured at each of the transceiver simultaneously. This will also create deterministic phase differences between transceivers, | ||
resources/eval/user-guides/adrv9009-zu11eg/syncronization.1623759751.txt.gz · Last modified: 15 Jun 2021 14:22 by Michael Hennerich