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--- resources:eval:user-guides:adrv9009-zu11eg:syncronization [04 Feb 2021 12:36] – [Theory of Operation] Michael Hennerich
+++ resources:eval:user-guides:adrv9009-zu11eg:syncronization [21 Feb 2024 09:06] (current) – [Reference distribution] Michael Hennerich
@@ Line 1: / Line 1: @@
 ====== ADRV9009-ZU11EG Multi-SOM Synchronization ======
-....
+===== Clock tree synchronization considerations =====
+The HMC7044 used throughout the entire clock-tree in this design supports two alternative synchronizations modes and methods. Both modes may have their own benefits and tradeoffs, such as:
+  * Jitter
+  * Correlated Close in Phase Noise
+  * Timing Requirements
+  * Phase Synchronization reliability over PVT
+  * Unwanted Signal Coupling
+  * Thermal Drift
+  * Power Consumption
+  * etc.
+We recommend planning for and evaluating both options.
+We provide device-trees for both methods.
+==== Reference distribution ====
+{{ :resources:eval:user-guides:adrv9009-zu11eg:reference_distribution.jpg?600 |}}
+A lower frequency reference is used between different levels in the clock tree (Inter-stage Frequency). All clock-chips in the hierarchy require its own local VCXO and this reference is used to lock the VCXO using PLL1 to the external reference. Any of the four available reference inputs ''CLKINx'' can be used in this mode.
+A additional ''SYNC'' signals is used to generate the synchronization event. If the ''SYNC'' pin transitions from 0 to 1 with sufficient setup/hold margin with respect to the VCXO, this synchronization event is deterministically carried through PLL2, up the timing chain through the N2 divider, and then to the master SYSREF timer. This mechanism of deterministic phase adjustment allows synchronization of the SYSREF timer and output phases of multiple HMC7044 devices. Please see the datasheet chapter “**Multichip Synchronization via PLL2**" For further details.
+^ Function ^ File ^
+| dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-jesd204-fsm-multisom-primary.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-jesd204-fsm-multisom-primary.dts]] |
+| dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-jesd204-fsm-multisom-secondary.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-jesd204-fsm-multisom-secondary.dts]] |
+| dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-primary.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-primary.dts]] |
+| dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-secondary.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-secondary.dts]] |
+<note warning>
+Depending on the Linux/Devicetree version, the HMC7044 eval board got replaced by [[resources:eval:user-guides:ad-synchrona14-ebz|AD-SYNCHRONA14-EBZ]] please see here:
+[[repo>linux/commit/ff537311d1fc7dc20d43a198b44007c22f2e9779]]
+<code>
+arch: arm64: adrv9009-zu11eg: Update hmc7044_ext
+To match default AD-SYNCHRONA14-EBZ configuration:
+CH8 - HMC7044 CLKOUT4 - CMOS
+CH10 - HMC7044 CLKOUT5 - LVPECL AC-COUPLED
+CH6 - HMC7044 CLKOUT6 - CMOS
+CH9 - HMC7044 CLKOUT12 - LVPECL AC-COUPLED
+</code>
+</note>
+==== Clock distribution ====
+{{ :resources:eval:user-guides:adrv9009-zu11eg:clock_distribution.png?600 |}}
+The maximum frequency used in the system is generated by the topmost HMC7044 and then distributed throughout the entire clock tree (Inter-stage Frequency).
+This method bypasses the PLL1 and PLL2 of all clock chips below the TOP chip. All lower level clock-chips act as clock fanout buffers, where only the clock distribution network output dividers can be used.
+This method is referred as **clock distribution**. All lower level clock-chips receive their input clock via ''FIN''/CLKIN1 and are synced via ''RFSYNC''/CLKIN0.
+<note tip>This mode also allows for TRX baseband rates that would be otherwise not possible with the default installed VCXO of 122.880MHz. Let's say someone needs exactly 250.000MSPS. This becomes possible by providing a 500.000MHz or 1000.000MHz external clock.</note>
+Depending on your [[resources:eval:user-guides:adrv9009-zu11eg:adrv2crr-fmc_carrier_board|ADRV2CRR-FMC]] Carrier Board Hardware revision following stuffing options need to be checked. These are required to route ''RFSYNC'' DC coupled to the from SMA connectors J5 RFSYNC_P, J6 RFSYNC_N to the HMC7044 ''RFSYNC'' input.
+<note important>Rev C:
+  * Replace C18, C19, C236, C240 with 0 Ohm resistors
+  * Replace C289, C290 with 0 Ohm resistors
+  * Unload 0 Ohm resistors from location R77, R112 and insert to R110, R111
+Rev C.1:
+  * Replace C289, C290 with 0 Ohm resistors
+  * Unload 0 Ohm resistors from location R77, R112 and insert to R110, R111
+</note>
+^ Function ^ File ^
+| dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-primary-clockdist.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-primary-clockdist.dts]] |
+| dts | [[linux.github>master?arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-secondary-clockdist.dts | zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-multisom-secondary-clockdist.dts]] |
 ===== Hardware setup =====
@@ Line 29: / Line 97: @@
         -CLKOUT5_P and CLKOUT6_P connect to the SYNC SMAs on the carrier
         -CLKOUT0 and CLKOUT2 connect to the REFCLK SMAs on the carrier
+<WRAP important>Only the following outputs work as SYNC in CMOS mode: CLKOUT0,3,5,6,9,10 and 13.
+The other outputs are 180deg out of phase in CMOS mode and should be used as differential REFCLOCK.</WRAP>
 {{ :resources:eval:user-guides:adrv9009_zu11eg:HMC7044_2.jpg?800 |}}
 ===== Software =====
-  * 11/09/2020
+  * [[:resources:tools-software:linux-software:kuiper-linux |Analog Devices Kuiper Linux]]
-    * {{ :resources:eval:user-guides:adrv9009-zu11eg:adrv9009_zu11eg_fmcomms8_nov9_2020.zip |ADRV9009-ZU11EG+FMCOMMMS8 Boot Files}}
 <note tip>The board which connects the external HMC7044 clockchip is refered as **primary** and requires the devicetree (system.dtb) from the primary folder in the archive. Likewise the board without the external clockchip connected is called **secondary**, and requires the devicetree from the secondary folder.</note>
@@ Line 43: / Line 112: @@
 There are two domains of synchronization that are considered in this configuration, the ADRV9009 transceivers and the FPGAs. Synchronization for the transceivers is provided by the clocking tree of HMC7044s and the JESD protocol. In the diagram several HMC7044s are cascade from a parent, or what we call external HMC7044, who is responsible for general system reference (sysref) control. These reference signals feed the clock chips on the individual SOMs and FPGAs.
-{{ :resources:eval:user-guides:adrv9009_zu11eg:talise_clocking_tree.png?nolink&400 |talise_clocking_tree}}
+The System Clocking Tree Diagram is located here:
+{{ :resources:eval:user-guides:adrv9009-zu11eg:adrv9009_rfsom_clocking_tree.png?direct&400 |ADRV9009-ZU11EG Clock Tree}}
 During multi-chip synchronization (MCS), which is a feature of the ADRV9009s, all baseband data from the converters is synchronized across transceiver chips. This requires specific sysrefs to be captured at each of the transceiver simultaneously. This will also create deterministic phase differences between transceivers, when RFPLL sync is enabled, as well. The individual API rights to the transceivers, clock chips, and their sequences are detailed in the rx method of the python class [[https://github.com/analogdevicesinc/pyadi-iio/blob/master/adi/adrv9009_zu11eg_multi.py|adrv9009_zu11eg_multi.py]].
@@ Line 64: / Line 134: @@
 </note>
+=== Synchronization at the application layer ===
+Synchronization at the application layer across multiple FPGAs is achieved using the external synchronization feature of the transport layer cores and using the SYSREF signal as the external synchronization signal.
+  * [[:resources:fpga:peripherals:jesd204:jesd204_tpl_adc#external_synchronization | ADC JESD204B/C Transport Peripheral - External synchronization]]
+  * [[:resources:fpga:peripherals:jesd204:jesd204_tpl_dac#external_synchronization | DAC JESD204B/C Transport Peripheral - External synchronization]]
+Once the JESD links are up the SYSREF pulses are no longer required from the JESD link perspective. However later assertions of the SYSREF pulses must respect the timing of the initial pulses in terms of phase and frequency to match the LMCF/LEMC of the link layer. These later SYSREF pulses can be used as references for simultaneous data capture/drive on multiple FPGAs. \\
+The synchronization mechanism must be orchestrated by software, software must disable the SYSREF generation to FPGAs before arming the external synchronization mechanisms from all the transport layer cores from all FPGAs, it must program all DMA cores to prepare moving data to or from system memory depending on direction, then software must program the clock chips for a single SYSREF pulse that will reach the transport layer cores simultaneously.

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