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--- resources:eval:user-guides:adrv9009-zu11eg:syncronization [27 May 2021 15:52] – [Theory of Operation] Laszlo Nagy
+++ resources:eval:user-guides:adrv9009-zu11eg:syncronization [15 Jun 2021 14:32] – [Clock distribution] Michael Hennerich
@@ Line 1: / Line 1: @@
 ====== ADRV9009-ZU11EG Multi-SOM Synchronization ======
-....
+===== Clock tree synchronization considerations =====
+The HMC7044 used throughout the entire clock-tree in this design supports two alternative synchronizations modes and methods. Both modes may have their own benefits and tradeoffs, such as Jitter, Correlated Close in Phase Noise, Timing Requirements, Phase Synchronization reliability over PVT, unwanted Signal Coupling, Thermal Drift, Power Consumption, etc.\\
+We recommend planning for and evaluating both options.
+We provide device-trees for both methods.
+==== Reference distribution ====
+{{ :resources:eval:user-guides:adrv9009-zu11eg:reference_distribution.jpg?600 |}}
+A lower frequency reference is used between different levels in the clock tree (Inter-stage Frequency). All clock-chips in the hierarchy require its own local VCXO and this reference is used to lock the VCXO using PLL1 to the external reference. Any of the four available reference inputs ''CLKINx'' can be used in this mode.
+A additional ''SYNC'' signals is used to generate the synchronization event. If the ''SYNC'' pin transitions from 0 to 1 with sufficient setup/hold margin with respect to the VCXO, this synchronization event is deterministically carried through PLL2, up the timing chain through the N2 divider, and then to the master SYSREF timer. This mechanism of deterministic phase adjustment allows synchronization of the SYSREF timer and output phases of multiple HMC7044 devices. Please see the datasheet chapter “**Multichip Synchronization via PLL2**" For further details.
+==== Clock distribution ====
+{{ :resources:eval:user-guides:adrv9009-zu11eg:clock_distribution.png?600 |}}
+The maximum frequency used in the system is generated by the topmost HMC7044 and then distributed throughout the entire clock tree (Inter-stage Frequency).
+This method bypasses the PLL1 and PLL2 of all clock chips below the TOP chip. All lower level clock-chips act as clock fanout buffers, where only the clock distribution network output dividers can be used.
+This method is referred as **clock distribution**. All lower level clock-chips receive their input clock via ''FIN''/CLKIN1 and are synced via ''RFSYNC''/CLKIN0.
+Depending on your [[resources:eval:user-guides:adrv9009-zu11eg:adrv2crr-fmc_carrier_board|ADRV2CRR-FMC]] Carrier Board Hardware revision following stuffing options need to be checked.
+| C289 | bypass/short |
+| C290 | bypass/short |
+| R110 | insert/short |
+| R111 | insert/short |
 ===== Hardware setup =====

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