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--- resources:eval:user-guides:adrv9009-zu11eg:syncronization [15 Jun 2021 14:51] – [Reference distribution] Michael Hennerich
+++ resources:eval:user-guides:adrv9009-zu11eg:syncronization [17 Jun 2021 09:22] – [Clock distribution] Michael Hennerich
@@ Line 38: / Line 38: @@
 This method is referred as **clock distribution**. All lower level clock-chips receive their input clock via ''FIN''/CLKIN1 and are synced via ''RFSYNC''/CLKIN0.
-Depending on your [[resources:eval:user-guides:adrv9009-zu11eg:adrv2crr-fmc_carrier_board|ADRV2CRR-FMC]] Carrier Board Hardware revision following stuffing options need to be checked.
+<note tip>This mode also allows for TRX baseband rates that would be otherwise not possible with the default installed VCXO of 122.880MHz. Let's say someone needs exactly 250.000MSPS. This becomes possible by providing a 500.000MHz or 1000.000MHz external clock.</note>
+Depending on your [[resources:eval:user-guides:adrv9009-zu11eg:adrv2crr-fmc_carrier_board|ADRV2CRR-FMC]] Carrier Board Hardware revision following stuffing options need to be checked. These are required to route ''RFSYNC'' DC coupled to the from SMA connectors J5 RFSYNC_P, J6 RFSYNC_N to the HMC7044 ''RFSYNC'' input.
 | C289 | bypass/short |

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