Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
resources:eval:user-guides:ade9430 [03 Jun 2022 21:08] – [Register List] David Lathresources:eval:user-guides:ade9430 [09 Apr 2024 16:32] (current) – Fixed voltage transfer function equation John Stuart
Line 1825: Line 1825:
  
 ====== Waveform Buffer ====== ====== Waveform Buffer ======
-<note important>SECTION NEEDS REVIEW John Stuart</note> 
 \\ \\
 \\ \\
Line 1899: Line 1898:
  
  
-<note important>need to verify if all the registers are correct all trigger modes removed</note> 
 \\ \\
 \\ \\
Line 1915: Line 1913:
 The waveform buffer contains 2048, 32-bit memory locations and can hold 512 (2048/4) sets of samples in coherent fill mode. In the ADE9430, the buffer is filled with 128 resampled points per line cycle, which implies that the buffer can hold four line cycles’ worth of data at any instant in time(128 × 4 = 512). With a 50 Hz line frequency, the buffer contains 80 ms worth of resampled data. The waveform buffer contains 2048, 32-bit memory locations and can hold 512 (2048/4) sets of samples in coherent fill mode. In the ADE9430, the buffer is filled with 128 resampled points per line cycle, which implies that the buffer can hold four line cycles’ worth of data at any instant in time(128 × 4 = 512). With a 50 Hz line frequency, the buffer contains 80 ms worth of resampled data.
  
-To start filling the waveform buffer with resampled waveforms, first clear the WF_CAP_EN bit to disable the waveform buffer. Then clear the WF_CAP_SEL bit in the WFB_CFG register to select the resampled data to be stored in the waveform buffer. Finally, set the WF_CAP_EN bit to start the resampling process. The waveform buffer starts filling from its first address location, 0x800. When the waveform buffer is full, the COH_WFB_FULL bit of STATUS 0 goes high, which can be enabled to generate an interrupt on IRQ0. Note that this is the only status bit available for the resampled waveforms. The filling of the waveform buffer stops.+To start filling the waveform buffer with resampled waveforms, first clear the WF_CAP_EN bit to disable the waveform buffer. Then clear the WF_CAP_SEL bit in the WFB_CFG register to select the resampled data to be stored in the waveform buffer. Finally, set the WF_CAP_EN bit to start the resampling process. The waveform buffer starts filling from its first address location, 0x800. In 1024 point resampling mode, the COH_PAGE_RDY indicates that a page is full. While, in 128 point resampling mode, the COH_PAGE_RDY bit indicates the buffer is completely full. COH_PAGE_RDY can be enabled to generate an interrupt on IRQ0.
  
 To obtain a new set of resampled data, first clear the WF_CAP_EN bit in the WFB_CFG register to 0 and then set the bit back to 1. To obtain a new set of resampled data, first clear the WF_CAP_EN bit in the WFB_CFG register to 0 and then set the bit back to 1.
Line 2330: Line 2328:
 The current transfer function is 20/3000 = 0.0067 V rms/A rms. The current transfer function is 20/3000 = 0.0067 V rms/A rms.
  
-The voltage transfer function is 1/(900 + 1) = 0.001 V rms/A rms.+The voltage transfer function is 1/(990 + 1) = 0.001 V rms/A rms.
  
 The input at the current ADC pins is 0.0067 × 10 = 0.067 V rms. The input at the current ADC pins is 0.0067 × 10 = 0.067 V rms.
Line 2891: Line 2889:
 ^ | | 8 | VNOMA_EN | | Set this bit to use the nominal phase voltage rms, VNOM, in the computation of Phase A total apparent power, AVA. | 0x0 | R/W | ^ | | 8 | VNOMA_EN | | Set this bit to use the nominal phase voltage rms, VNOM, in the computation of Phase A total apparent power, AVA. | 0x0 | R/W |
 ^ | | 7 | RMS_SRC_SEL | | This bit selects which samples are used for the One-Cycle rms and 10 cycle rms/12 cycle rms calculation. | 0x0 | R/W | ^ | | 7 | RMS_SRC_SEL | | This bit selects which samples are used for the One-Cycle rms and 10 cycle rms/12 cycle rms calculation. | 0x0 | R/W |
-^ | | | | 0 | xI_PCF waveforms, after the high-pass filter and integrator. | | | +^ | | | | 0 | xI_PCF waveforms, after the high-pass filter. | | | 
-^ | | | | 1 | ADC samples, before the high-pass filter and integrator. | | | +^ | | | | 1 | ADC samples, before the high-pass filter. | | | 
-^ | | 6 | ZX_SRC_SEL | | This bit selects whether data going into the zero-crossing detection circuit comes before the high-pass filter, integrator, and phase compensation or afterwards. | 0x0 | R/W | +^ | | 6 | ZX_SRC_SEL | | This bit selects whether data going into the zero-crossing detection circuit comes before the high-pass filter, and phase compensation or afterwards. | 0x0 | R/W | 
-^ | | | | 0 | After the high-pass filter, integrator, and phase compensation. | | | +^ | | | | 0 | After the high-pass filter, and phase compensation. | | | 
-^ | | | | 1 | Before the high-pass filter, integrator, and phase compensation. | | | +^ | | | | 1 | Before the high-pass filter,  and phase compensation. | | | 
-^ | | 5 | INTEN | | Set this bit to enable the integrators in the phase current channels. The neutral current channel integrator is managed by the ININTEN bit in the CONFIG0 register. | 0x0 | R/W |+^ | | 5 |     RESERVED    | | RESERVED | 0x0 | R |
 ^ | | 4 | MTEN | | Set this bit to enable multipoint phase and gain compensation. If enabled, an additional gain factor, xIGAIN0 through xIGAIN5, is applied to the current channel based on the xIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. | 0x0 | R/W | ^ | | 4 | MTEN | | Set this bit to enable multipoint phase and gain compensation. If enabled, an additional gain factor, xIGAIN0 through xIGAIN5, is applied to the current channel based on the xIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. | 0x0 | R/W |
 ^ | | 3 | HPFDIS | | Set this bit to disable high-pass filters in all the voltage and current channels. | 0x0 | R/W | ^ | | 3 | HPFDIS | | Set this bit to disable high-pass filters in all the voltage and current channels. | 0x0 | R/W |
Line 3004: Line 3002:
 ^ | | 25 | TEMP_RDY_MASK | | Set this bit to enable an interrupt when a new temperature measurement is available. | 0x0 | R/W | ^ | | 25 | TEMP_RDY_MASK | | Set this bit to enable an interrupt when a new temperature measurement is available. | 0x0 | R/W |
 ^ | | 24 | MISMTCH | | Set this bit to enable an interrupt when there is a change in the relationship between ISUMRMS and ISUMLVL. | 0x0 | R/W | ^ | | 24 | MISMTCH | | Set this bit to enable an interrupt when there is a change in the relationship between ISUMRMS and ISUMLVL. | 0x0 | R/W |
-^ | | 23 | COH_PAGE_RDY | | This bit indicates that one page is full when using the 1024 point resampling mode. The COH_PAGE indicates which page is full. In 128 point resampling mode this bit indicates the buffer is completely full. | 0x0 | R/W |+^ | | 23 | COH_PAGE_RDY | | Set this bit to enable an interrupt when the waveform buffer is full of resampled data. | 0x0 | R/W |
 ^ | | 22 | WFB_TRIG | | Set this bit to enable an interrupt when one of the events configured in WFB_TRIG_CFG occurs. | 0x0 | R/W | ^ | | 22 | WFB_TRIG | | Set this bit to enable an interrupt when one of the events configured in WFB_TRIG_CFG occurs. | 0x0 | R/W |
 ^ | | 21 | PF_RDY | | Set this bit to enable an interrupt when the power factor measurements are updated, every 1.024 sec. | 0x0 | R/W | ^ | | 21 | PF_RDY | | Set this bit to enable an interrupt when the power factor measurements are updated, every 1.024 sec. | 0x0 | R/W |
Line 3197: Line 3195:
 ^ | | [1:0] | WATTACC | | Total and fundamental active power accumulation mode for energy registers and CFx pulses. See VARACC. | 0x0 | R/W | ^ | | [1:0] | WATTACC | | Total and fundamental active power accumulation mode for energy registers and CFx pulses. See VARACC. | 0x0 | R/W |
 ^ 0x493 | CONFIG3 | [15:12] | OC_EN | | Overcurrent detection enable. OC_EN[3:0] bits can all be set to 1 simultaneously to allow overcurrent detection on all three phases and/or neutral simultaneously. | 0xF | R/W | ^ 0x493 | CONFIG3 | [15:12] | OC_EN | | Overcurrent detection enable. OC_EN[3:0] bits can all be set to 1 simultaneously to allow overcurrent detection on all three phases and/or neutral simultaneously. | 0xF | R/W |
-^ | | | | | Bit 12. When OC_EN[3] is set to 1, Phase A is selected for the overcurrent detection. | | | +^ | | | | | Bit 15. When OC_EN[3] is set to 1, Phase A is selected for the overcurrent detection. | | | 
-^ | | | | | Bit 13. When OC_EN[2] is set to 1, Phase B is selected for the overcurrent detection. | | | +^ | | | | | Bit 14. When OC_EN[2] is set to 1, Phase B is selected for the overcurrent detection. | | | 
-^ | | | | | Bit 14. When OC_EN[1] is set to 1, Phase C is selected for the overcurrent detection. | | | +^ | | | | | Bit 13. When OC_EN[1] is set to 1, Phase C is selected for the overcurrent detection. | | | 
-^ | | | | | Bit 15. When OC_EN[0] is set to 1, the neutral line is selected for the overcurrent detection. | | |+^ | | | | | Bit 12. When OC_EN[0] is set to 1, the neutral line is selected for the overcurrent detection. | | |
 ^ | | [11:5] | RESERVED | | Reserved. | 0x0 | R | ^ | | [11:5] | RESERVED | | Reserved. | 0x0 | R |
 ^ | | [4:2] | PEAKSEL | | Set this bit to select which phase(s) to monitor peak voltages and currents on. Write 1 to PEAKSEL, Bit 0 to enable Phase A peak detection. Similarly, PEAKSEL, Bit 1 enables Phase B peak detection, and PEAKSEL, Bit 2 enables Phase C peak detection. | 0x0 | R/W | ^ | | [4:2] | PEAKSEL | | Set this bit to select which phase(s) to monitor peak voltages and currents on. Write 1 to PEAKSEL, Bit 0 to enable Phase A peak detection. Similarly, PEAKSEL, Bit 1 enables Phase B peak detection, and PEAKSEL, Bit 2 enables Phase C peak detection. | 0x0 | R/W |
resources/eval/user-guides/ade9430.1654283308.txt.gz · Last modified: 03 Jun 2022 21:08 by David Lath

Page Tools