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resources:eval:user-guides:ade9430 [28 Apr 2022 21:36] – [Burst Read Waveform Buffer Samples from SPI] David Smithresources:eval:user-guides:ade9430 [09 Apr 2024 16:32] (current) – Fixed voltage transfer function equation John Stuart
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 xIGAIN = ROUND[(−1 − 1) × 2<sup>27</sup>] = −268435456 = 0xF000_0000 xIGAIN = ROUND[(−1 − 1) × 2<sup>27</sup>] = −268435456 = 0xF000_0000
  
-If the multipoint phase and gain feature is used, it is recommended to use the xIGAIN for the main correction, done at the nominal current for the meter ([[resources:eval:user-guides:ADE9430#Multipoint Phase/Gain Calibration|see the Multipoint Phase/Gain Calibration section for more information]]).+If the multipoint phase and gain feature is used, it is recommended to use the xIGAIN for the primary correction, done at the nominal current for the meter ([[resources:eval:user-guides:ADE9430#Multipoint Phase/Gain Calibration|see the Multipoint Phase/Gain Calibration section for more information]]).
  
 Note that for a given phase, Note that for a given phase,
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-The ADE9430 has a SPI-compatible interface, consisting of four pins: SCLK, MOSI, MISO, and SS. The ADE9430 is always a SPI slave; it never initiates SPI communication. The SPI interface is compatible with 16-bit and 32-bit read/write operations. See the [[resources:eval:user-guides:ADE9430#Register List|Register Information section]] for information about the length of each register.+The ADE9430 has a SPI-compatible interface, consisting of four pins: SCLK, MOSI, MISO, and SS. The ADE9430 is always a SPI subordinate; it never initiates SPI communication. The SPI interface is compatible with 16-bit and 32-bit read/write operations. See the [[resources:eval:user-guides:ADE9430#Register List|Register Information section]] for information about the length of each register.
  
-Figure 38. shows the connection between the ADE9430 SPI and a master device that contains a SPI interface.+Figure 38. shows the connection between the ADE9430 SPI and a main device that contains a SPI interface.
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-{{ :resources:eval:user-guides:connecting_the_ade9430_slave_spi_port_to_a_master_spi_device1.svg? 500 x 500 |}} +{{ :resources:eval:user-guides:connecting_the_ade9430_sub_spi_port_to_a_main_spi_device1.svg |}} 
-<WRAP centeralign>**Figure 38. Connecting the ADE9430 Slave SPI Port to a Master SPI Device**</WRAP>+<WRAP centeralign>**Figure 38. Connecting the ADE9430 Subordinate SPI Port to a Main SPI Device**</WRAP>
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 The SS input must stay low for the whole SPI transaction. Bringing SS high during a data transfer operation aborts the transfer. A new transfer can be initiated by returning the SS logic input low. It is not recommended to tie SS to ground because the high to low transition on SS starts the ADE9430 SPI transaction. The SS input must stay low for the whole SPI transaction. Bringing SS high during a data transfer operation aborts the transfer. A new transfer can be initiated by returning the SS logic input low. It is not recommended to tie SS to ground because the high to low transition on SS starts the ADE9430 SPI transaction.
  
-Data shifts into the device at the MOSI logic input on the falling edge of SCLK, and the device samples the input data on the rising edge of SCLK. Data shifts out of the ADE9430 at the MISO logic output on the falling edge of SCLK and must be sampled by the master device on the rising edge of SCLK. The most significant bit of the word is shifted in and out first.+Data shifts into the device at the MOSI logic input on the falling edge of SCLK, and the device samples the input data on the rising edge of SCLK. Data shifts out of the ADE9430 at the MISO logic output on the falling edge of SCLK and must be sampled by the main device on the rising edge of SCLK. The most significant bit of the word is shifted in and out first.
  
 MISO has an internal weak pull-up of 100 kΩ, making the default state of the MISO pin high. It is possible to share the SPI bus with multiple devices, including multiple ADE9430 devices, if desired. MISO has an internal weak pull-up of 100 kΩ, making the default state of the MISO pin high. It is possible to share the SPI bus with multiple devices, including multiple ADE9430 devices, if desired.
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-The default state of the MOSI pin depends on the master SPI device. Here, it is assumed to be high (Logic 1).+The default state of the MOSI pin depends on the main SPI device. Here, it is assumed to be high (Logic 1).
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 The 16-bit or 32-bit data to be written follows the command header, with the most significant bit first. The 16-bit or 32-bit data to be written follows the command header, with the most significant bit first.
  
-After the last bit of data has been clocked out, the master must bring the SS line high to release the SPI bus. It is recommended to have the SCLK line idle high.+After the last bit of data has been clocked out, the main device must bring the SS line high to release the SPI bus. It is recommended to have the SCLK line idle high.
  
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 The SS line can be brought high before clocking out the CRC if this information is not needed in the application. The SS line can be brought high before clocking out the CRC if this information is not needed in the application.
  
-After the last bit of data, or CRC, has been clocked out, the master must bring the SS line high to release the SPI bus. Then the ADE9430 stops driving MISO and enables a 100 kΩ weak pull-up. It is recommended to have the SCLK line idle high.+After the last bit of data, or CRC, has been clocked out, the main device must bring the SS line high to release the SPI bus. Then the ADE9430 stops driving MISO and enables a 100 kΩ weak pull-up. It is recommended to have the SCLK line idle high.
  
 An example of what happens when reading the AVGAIN register, Address 0x00B, when BURST_EN = 0 and 1 is shown in Figure 42. An example of what happens when reading the AVGAIN register, Address 0x00B, when BURST_EN = 0 and 1 is shown in Figure 42.
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 A burst read operation using the SPI interface of the ADE9430 is initiated when the SS pin goes low and the ADE9430 receives a 16-bit command header (CMD_HDR) with CMD_HDR[3] equal to 1, which meets the criteria in Table 20 where next address is shown. A burst read operation using the SPI interface of the ADE9430 is initiated when the SS pin goes low and the ADE9430 receives a 16-bit command header (CMD_HDR) with CMD_HDR[3] equal to 1, which meets the criteria in Table 20 where next address is shown.
  
-Following the command header, ADE9430 sends the register data for the register addressed in the command. After the last bit of the first register value is received, the ADE9430 auto-increments the address and starts clocking out the data from the next register address. If the starting address is in the range of Address 0x500 to Address 0x516 and the SPI is clocked beyond Address 0x516, the address is auto-incremented until it reaches Address 0x5FF and then wraps back to the initial address. If the initial address is in the Address 0x600 to Address 0x63C or Address 0x680 to Address 0x6BC range and the SPI is clocked beyond Address 0x63C or Address 0x6BC, the address wraps back to the initial address. This process continues until the master sets the SS line high. Then, the ADE9430 stops driving MISO and enables a 100 kΩ weak pull-up. It is recommended to have the SCLK line idle high. An example of a SPI burst read operation is shown in Figure 39, when BURST_EN = 1. For other examples, see the [[resources:eval:user-guides:ADE9430#Burst Read Waveform Buffer Samples from SPI|Burst Read Waveform Buffer Samples from SPI section]].+Following the command header, ADE9430 sends the register data for the register addressed in the command. After the last bit of the first register value is received, the ADE9430 auto-increments the address and starts clocking out the data from the next register address. If the starting address is in the range of Address 0x500 to Address 0x516 and the SPI is clocked beyond Address 0x516, the address is auto-incremented until it reaches Address 0x5FF and then wraps back to the initial address. If the initial address is in the Address 0x600 to Address 0x63C or Address 0x680 to Address 0x6BC range and the SPI is clocked beyond Address 0x63C or Address 0x6BC, the address wraps back to the initial address. This process continues until the main device sets the SS line high. Then, the ADE9430 stops driving MISO and enables a 100 kΩ weak pull-up. It is recommended to have the SCLK line idle high. An example of a SPI burst read operation is shown in Figure 39, when BURST_EN = 1. For other examples, see the [[resources:eval:user-guides:ADE9430#Burst Read Waveform Buffer Samples from SPI|Burst Read Waveform Buffer Samples from SPI section]].
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-The ADE9430 SPI port calculates a CRC of the data sent out on its MOSI pin so that the integrity of the data received by the master can be checked. The CRC of the data sent out on the MOSI pin during the last register read is offered in a 16-bit register, CRC_SPI, and can be appended to the SPI read data as part of the SPI transaction.+The ADE9430 SPI port calculates a CRC of the data sent out on its MOSI pin so that the integrity of the data received by the main device can be checked. The CRC of the data sent out on the MOSI pin during the last register read is offered in a 16-bit register, CRC_SPI, and can be appended to the SPI read data as part of the SPI transaction.
  
 The CRC_SPI register value is appended to the 16-/32-bit data read from the register addressed in the CMD_HDR for the cases in Table 20 where CRC is written see the [[resources:eval:user-guides:ADE9430#SPI Read|SPI Read section]] for more information. The CRC_SPI register value is appended to the 16-/32-bit data read from the register addressed in the CMD_HDR for the cases in Table 20 where CRC is written see the [[resources:eval:user-guides:ADE9430#SPI Read|SPI Read section]] for more information.
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 The LAST_CMD register is updated after the CMD_HDR is received. If a command to read the LAST_CMD, LAST_DATA_16, or LAST_DATA_32 registers is received, these three registers are not updated. Note that LAST_CMD[2:0] always reads back as 000. The LAST_CMD register is updated after the CMD_HDR is received. If a command to read the LAST_CMD, LAST_DATA_16, or LAST_DATA_32 registers is received, these three registers are not updated. Note that LAST_CMD[2:0] always reads back as 000.
  
-During a SPI read operation, the LAST_DATA_16 and LAST_DATA_32 registers are updated within two master clocks after the CMD_HDR has been received. If a command to read the LAST_CMD, LAST_DATA_16, or LAST_DATA_32 registers is received, these three registers are not updated.+During a SPI read operation, the LAST_DATA_16 and LAST_DATA_32 registers are updated within two main clocks after the CMD_HDR has been received. If a command to read the LAST_CMD, LAST_DATA_16, or LAST_DATA_32 registers is received, these three registers are not updated.
  
 Note that the LAST_DATA_16 and LAST_DATA_32 registers are not updated after a SPI burst read operation; these are the cases in Table 20 where next address is written. Note that the LAST_DATA_16 and LAST_DATA_32 registers are not updated after a SPI burst read operation; these are the cases in Table 20 where next address is written.
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 ====== Waveform Buffer ====== ====== Waveform Buffer ======
-<note important>SECTION NEEDS REVIEW John Stuart</note> 
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-<note important>need to verify if all the registers are correct all trigger modes removed</note> 
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 The waveform buffer contains 2048, 32-bit memory locations and can hold 512 (2048/4) sets of samples in coherent fill mode. In the ADE9430, the buffer is filled with 128 resampled points per line cycle, which implies that the buffer can hold four line cycles’ worth of data at any instant in time(128 × 4 = 512). With a 50 Hz line frequency, the buffer contains 80 ms worth of resampled data. The waveform buffer contains 2048, 32-bit memory locations and can hold 512 (2048/4) sets of samples in coherent fill mode. In the ADE9430, the buffer is filled with 128 resampled points per line cycle, which implies that the buffer can hold four line cycles’ worth of data at any instant in time(128 × 4 = 512). With a 50 Hz line frequency, the buffer contains 80 ms worth of resampled data.
  
-To start filling the waveform buffer with resampled waveforms, first clear the WF_CAP_EN bit to disable the waveform buffer. Then clear the WF_CAP_SEL bit in the WFB_CFG register to select the resampled data to be stored in the waveform buffer. Finally, set the WF_CAP_EN bit to start the resampling process. The waveform buffer starts filling from its first address location, 0x800. When the waveform buffer is full, the COH_WFB_FULL bit of STATUS 0 goes high, which can be enabled to generate an interrupt on IRQ0. Note that this is the only status bit available for the resampled waveforms. The filling of the waveform buffer stops.+To start filling the waveform buffer with resampled waveforms, first clear the WF_CAP_EN bit to disable the waveform buffer. Then clear the WF_CAP_SEL bit in the WFB_CFG register to select the resampled data to be stored in the waveform buffer. Finally, set the WF_CAP_EN bit to start the resampling process. The waveform buffer starts filling from its first address location, 0x800. In 1024 point resampling mode, the COH_PAGE_RDY indicates that a page is full. While, in 128 point resampling mode, the COH_PAGE_RDY bit indicates the buffer is completely full. COH_PAGE_RDY can be enabled to generate an interrupt on IRQ0.
  
 To obtain a new set of resampled data, first clear the WF_CAP_EN bit in the WFB_CFG register to 0 and then set the bit back to 1. To obtain a new set of resampled data, first clear the WF_CAP_EN bit in the WFB_CFG register to 0 and then set the bit back to 1.
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 ==== Example 1: Fixed Data Rate Data, Seven Channel Samples ==== ==== Example 1: Fixed Data Rate Data, Seven Channel Samples ====
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-WFB_CAP_SEL = 1, WF_IN_EN = 1, and BURST_CHAN = 0000 in the WFB_CFG register indicates that there is fixed data rate data in the waveform buffer and the user wants to read out samples from all seven channels. A command is sent to read Address 0x801, which is interpreted as a read to the sample set starting at Address 0x800. The first 32 SPI clocks return IA from Address 0x800, followed by VA from Address 0x801, and so on, until IN from Address 0x806. Then the sample set auto-increments and the next data is IA from Address 0x808, followed by VA. This example is shown in Figure 49. The default state of the MOSI pin depends on the master SPI device; in Figure 49, it is assumed to be high (Logic 1).+WFB_CAP_SEL = 1, WF_IN_EN = 1, and BURST_CHAN = 0000 in the WFB_CFG register indicates that there is fixed data rate data in the waveform buffer and the user wants to read out samples from all seven channels. A command is sent to read Address 0x801, which is interpreted as a read to the sample set starting at Address 0x800. The first 32 SPI clocks return IA from Address 0x800, followed by VA from Address 0x801, and so on, until IN from Address 0x806. Then the sample set auto-increments and the next data is IA from Address 0x808, followed by VA. This example is shown in Figure 49. The default state of the MOSI pin depends on the main SPI device; in Figure 49, it is assumed to be high (Logic 1).
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 ==== Example2: Resampled Data, Phase C (I and V samples) ==== ==== Example2: Resampled Data, Phase C (I and V samples) ====
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-WFB_CAP_SEL = 0 and BURST_CHAN = 0011 in the WFB_CFG register indicates that there is resampled data in the waveform buffer and the user wants to read out IC and VC samples. A command is sent to read Address 0x801, which is interpreted as a read to the sample set starting at Address 0x800. VC waveform from Address 0x802 is first transferred, followed by IC from Address 0x802. Then the sample set auto-increments and the next data is VC from Address 0x806, followed by IC from the same address, then VC from Address 0x80A and IC from Address 0x80A, and so on see Figure 50. The default state of the MOSI pin depends on the master SPI device; in Figure 50, it is assumed to be high (Logic 1).+WFB_CAP_SEL = 0 and BURST_CHAN = 0011 in the WFB_CFG register indicates that there is resampled data in the waveform buffer and the user wants to read out IC and VC samples. A command is sent to read Address 0x801, which is interpreted as a read to the sample set starting at Address 0x800. VC waveform from Address 0x802 is first transferred, followed by IC from Address 0x802. Then the sample set auto-increments and the next data is VC from Address 0x806, followed by IC from the same address, then VC from Address 0x80A and IC from Address 0x80A, and so on see Figure 50. The default state of the MOSI pin depends on the main SPI device; in Figure 50, it is assumed to be high (Logic 1).
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 ==== Example 3: Fixed Data Rate Data, Single Address Read Mode ==== ==== Example 3: Fixed Data Rate Data, Single Address Read Mode ====
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-WFB_CAP_SEL = 1 and BURST_CHAN = 1111 in the WFB_CFG register indicates that there is fixed data rate data in the waveform buffer and the user wants to read out one single address. A command is sent to read Address 0x801, which is interpreted as a read to Address 0x801. VA waveform from Address 0x801 is transferred, followed by the CRC if BURST_EN = 0. If BURST_EN = 1, the VA waveform data from Address 0x801 is repeated again. This example is shown in Figure 51. The default state of the MOSI pin depends on the master SPI device; in Figure 51, it is assumed to be high (Logic 1). The transfer of data continues as long as the CS line is kept low and SCLK clocks arrive at the ADE9430 SCLK pin.+WFB_CAP_SEL = 1 and BURST_CHAN = 1111 in the WFB_CFG register indicates that there is fixed data rate data in the waveform buffer and the user wants to read out one single address. A command is sent to read Address 0x801, which is interpreted as a read to Address 0x801. VA waveform from Address 0x801 is transferred, followed by the CRC if BURST_EN = 0. If BURST_EN = 1, the VA waveform data from Address 0x801 is repeated again. This example is shown in Figure 51. The default state of the MOSI pin depends on the main SPI device; in Figure 51, it is assumed to be high (Logic 1). The transfer of data continues as long as the CS line is kept low and SCLK clocks arrive at the ADE9430 SCLK pin.
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 The current transfer function is 20/3000 = 0.0067 V rms/A rms. The current transfer function is 20/3000 = 0.0067 V rms/A rms.
  
-The voltage transfer function is 1/(900 + 1) = 0.001 V rms/A rms.+The voltage transfer function is 1/(990 + 1) = 0.001 V rms/A rms.
  
 The input at the current ADC pins is 0.0067 × 10 = 0.067 V rms. The input at the current ADC pins is 0.0067 × 10 = 0.067 V rms.
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 ===== Register List ===== ===== Register List =====
-add this info then remove 
- 
-John Stuart are these register for the users? 
-<note important> 
-^ Item ^ Address ^ Compared to ADE9000 ^ Description ^ 
-| PERIOD_FORRMS | 0x26B | Newly added | The snapshotted version of the Tensilica input “PERIOD”. | 
-| | | | more details refer to: ADE9430 firmware specification | 
-| COH_PAGE | 0x26C | Newly added | The page (first half or second half) which is full/ready-to-read during the resampling waveform fill. | 
-| | | | more details refer to: ADE9430 firmware specification | 
-| RESAMPLE_STATUS | 0x26D | Newly added | The synced version of "resample_en". | 
-</note> 
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 ^ 0x269 | ISUMRMS | Filter-based rms based on the sum of IA + IB + IC ± IN. | 0x00000000 | R | ^ 0x269 | ISUMRMS | Filter-based rms based on the sum of IA + IB + IC ± IN. | 0x00000000 | R |
 ^ 0x26A | VERSION2 | This register indicates the version of the metrology algorithms after the user writes run = 1 to start the measurements. | 0x0000000C | R | ^ 0x26A | VERSION2 | This register indicates the version of the metrology algorithms after the user writes run = 1 to start the measurements. | 0x0000000C | R |
 +^ 0x26B | PERIOD_FORRMS | This is a copy of the PERIOD register that is synchronized to the cycle based RMS, updated every half-cycle. | 0x00000000 | R |
 +^ 0x26C | COH_PAGE | This indicates the page that is full and ready to read during the resampled waveform fill. 0: first half of buffer is ready to read. 1: second half of buffer is ready to read. | 0x00000000 | R |
 +^ 0x26D | RESAMPLE_STATUS | This register indicates that resampling has started. Resampling will start on the first 10/12 cycle boundary after WFB_CFG. WF_CAP_EN is set to 1 | 0x00000000 | R |
 ^ 0x2E5 | AWATT_ACC | Phase A accumulated total active power, updated after PWR_TIME 8 kSPS samples. | 0x00000000 | R | ^ 0x2E5 | AWATT_ACC | Phase A accumulated total active power, updated after PWR_TIME 8 kSPS samples. | 0x00000000 | R |
 ^ 0x2E6 | AWATTHR_LO | Phase A accumulated total active energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. | 0x00000000 | R | ^ 0x2E6 | AWATTHR_LO | Phase A accumulated total active energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. | 0x00000000 | R |
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 ^ | | 8 | VNOMA_EN | | Set this bit to use the nominal phase voltage rms, VNOM, in the computation of Phase A total apparent power, AVA. | 0x0 | R/W | ^ | | 8 | VNOMA_EN | | Set this bit to use the nominal phase voltage rms, VNOM, in the computation of Phase A total apparent power, AVA. | 0x0 | R/W |
 ^ | | 7 | RMS_SRC_SEL | | This bit selects which samples are used for the One-Cycle rms and 10 cycle rms/12 cycle rms calculation. | 0x0 | R/W | ^ | | 7 | RMS_SRC_SEL | | This bit selects which samples are used for the One-Cycle rms and 10 cycle rms/12 cycle rms calculation. | 0x0 | R/W |
-^ | | | | 0 | xI_PCF waveforms, after the high-pass filter and integrator. | | | +^ | | | | 0 | xI_PCF waveforms, after the high-pass filter. | | | 
-^ | | | | 1 | ADC samples, before the high-pass filter and integrator. | | | +^ | | | | 1 | ADC samples, before the high-pass filter. | | | 
-^ | | 6 | ZX_SRC_SEL | | This bit selects whether data going into the zero-crossing detection circuit comes before the high-pass filter, integrator, and phase compensation or afterwards. | 0x0 | R/W | +^ | | 6 | ZX_SRC_SEL | | This bit selects whether data going into the zero-crossing detection circuit comes before the high-pass filter, and phase compensation or afterwards. | 0x0 | R/W | 
-^ | | | | 0 | After the high-pass filter, integrator, and phase compensation. | | | +^ | | | | 0 | After the high-pass filter, and phase compensation. | | | 
-^ | | | | 1 | Before the high-pass filter, integrator, and phase compensation. | | | +^ | | | | 1 | Before the high-pass filter,  and phase compensation. | | | 
-^ | | 5 | INTEN | | Set this bit to enable the integrators in the phase current channels. The neutral current channel integrator is managed by the ININTEN bit in the CONFIG0 register. | 0x0 | R/W |+^ | | 5 |     RESERVED    | | RESERVED | 0x0 | R |
 ^ | | 4 | MTEN | | Set this bit to enable multipoint phase and gain compensation. If enabled, an additional gain factor, xIGAIN0 through xIGAIN5, is applied to the current channel based on the xIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. | 0x0 | R/W | ^ | | 4 | MTEN | | Set this bit to enable multipoint phase and gain compensation. If enabled, an additional gain factor, xIGAIN0 through xIGAIN5, is applied to the current channel based on the xIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. | 0x0 | R/W |
 ^ | | 3 | HPFDIS | | Set this bit to disable high-pass filters in all the voltage and current channels. | 0x0 | R/W | ^ | | 3 | HPFDIS | | Set this bit to disable high-pass filters in all the voltage and current channels. | 0x0 | R/W |
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 ^ | | 25 | TEMP_RDY | | This bit goes high to indicate when a new temperature measurement is available. | 0x0 | R/W1 | ^ | | 25 | TEMP_RDY | | This bit goes high to indicate when a new temperature measurement is available. | 0x0 | R/W1 |
 ^ | | 24 | MISMTCH | | This bit is set to indicate a change in the relationship between ISUMRMS and ISUMLVL. | 0x0 | R/W1 | ^ | | 24 | MISMTCH | | This bit is set to indicate a change in the relationship between ISUMRMS and ISUMLVL. | 0x0 | R/W1 |
-^ | | 23 | COH_WFB_FULL | | This bit is set when the waveform buffer is full with resampled data, which is selected when WF_CAP_SEL = 0 in the WFB_CFG register. | 0x0 | R/W1 |+^ | | 23 | COH_PAGE_RDY | | This bit indicates that one page is full when using the 1024 point resampling mode. The COH_PAGE indicates which page is full. In 128 point resampling mode this bit indicates the buffer is completely full. | 0x0 | R/W1 |
 ^ | | 22 | WFB_TRIG | | This bit is set when one of the events configured in WFB_TRIG_CFG occurs. | 0x0 | R/W1 | ^ | | 22 | WFB_TRIG | | This bit is set when one of the events configured in WFB_TRIG_CFG occurs. | 0x0 | R/W1 |
 ^ | | 21 | PF_RDY | | This bit goes high to indicate when the power factor measurements update, every 1.024 sec. | 0x0 | R/W1 | ^ | | 21 | PF_RDY | | This bit goes high to indicate when the power factor measurements update, every 1.024 sec. | 0x0 | R/W1 |
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 ^ | | 25 | TEMP_RDY_MASK | | Set this bit to enable an interrupt when a new temperature measurement is available. | 0x0 | R/W | ^ | | 25 | TEMP_RDY_MASK | | Set this bit to enable an interrupt when a new temperature measurement is available. | 0x0 | R/W |
 ^ | | 24 | MISMTCH | | Set this bit to enable an interrupt when there is a change in the relationship between ISUMRMS and ISUMLVL. | 0x0 | R/W | ^ | | 24 | MISMTCH | | Set this bit to enable an interrupt when there is a change in the relationship between ISUMRMS and ISUMLVL. | 0x0 | R/W |
-^ | | 23 | COH_WFB_FULL | | Set this bit to enable an interrupt when the waveform buffer is full with resampled data, which is selected when WF_CAP_SEL = 0 in the WFB_CFG register. | 0x0 | R/W |+^ | | 23 | COH_PAGE_RDY | | Set this bit to enable an interrupt when the waveform buffer is full of resampled data. | 0x0 | R/W |
 ^ | | 22 | WFB_TRIG | | Set this bit to enable an interrupt when one of the events configured in WFB_TRIG_CFG occurs. | 0x0 | R/W | ^ | | 22 | WFB_TRIG | | Set this bit to enable an interrupt when one of the events configured in WFB_TRIG_CFG occurs. | 0x0 | R/W |
 ^ | | 21 | PF_RDY | | Set this bit to enable an interrupt when the power factor measurements are updated, every 1.024 sec. | 0x0 | R/W | ^ | | 21 | PF_RDY | | Set this bit to enable an interrupt when the power factor measurements are updated, every 1.024 sec. | 0x0 | R/W |
Line 3205: Line 3195:
 ^ | | [1:0] | WATTACC | | Total and fundamental active power accumulation mode for energy registers and CFx pulses. See VARACC. | 0x0 | R/W | ^ | | [1:0] | WATTACC | | Total and fundamental active power accumulation mode for energy registers and CFx pulses. See VARACC. | 0x0 | R/W |
 ^ 0x493 | CONFIG3 | [15:12] | OC_EN | | Overcurrent detection enable. OC_EN[3:0] bits can all be set to 1 simultaneously to allow overcurrent detection on all three phases and/or neutral simultaneously. | 0xF | R/W | ^ 0x493 | CONFIG3 | [15:12] | OC_EN | | Overcurrent detection enable. OC_EN[3:0] bits can all be set to 1 simultaneously to allow overcurrent detection on all three phases and/or neutral simultaneously. | 0xF | R/W |
-^ | | | | | Bit 12. When OC_EN[3] is set to 1, Phase A is selected for the overcurrent detection. | | | +^ | | | | | Bit 15. When OC_EN[3] is set to 1, Phase A is selected for the overcurrent detection. | | | 
-^ | | | | | Bit 13. When OC_EN[2] is set to 1, Phase B is selected for the overcurrent detection. | | | +^ | | | | | Bit 14. When OC_EN[2] is set to 1, Phase B is selected for the overcurrent detection. | | | 
-^ | | | | | Bit 14. When OC_EN[1] is set to 1, Phase C is selected for the overcurrent detection. | | | +^ | | | | | Bit 13. When OC_EN[1] is set to 1, Phase C is selected for the overcurrent detection. | | | 
-^ | | | | | Bit 15. When OC_EN[0] is set to 1, the neutral line is selected for the overcurrent detection. | | |+^ | | | | | Bit 12. When OC_EN[0] is set to 1, the neutral line is selected for the overcurrent detection. | | |
 ^ | | [11:5] | RESERVED | | Reserved. | 0x0 | R | ^ | | [11:5] | RESERVED | | Reserved. | 0x0 | R |
 ^ | | [4:2] | PEAKSEL | | Set this bit to select which phase(s) to monitor peak voltages and currents on. Write 1 to PEAKSEL, Bit 0 to enable Phase A peak detection. Similarly, PEAKSEL, Bit 1 enables Phase B peak detection, and PEAKSEL, Bit 2 enables Phase C peak detection. | 0x0 | R/W | ^ | | [4:2] | PEAKSEL | | Set this bit to select which phase(s) to monitor peak voltages and currents on. Write 1 to PEAKSEL, Bit 0 to enable Phase A peak detection. Similarly, PEAKSEL, Bit 1 enables Phase B peak detection, and PEAKSEL, Bit 2 enables Phase C peak detection. | 0x0 | R/W |
resources/eval/user-guides/ade9430.1651174581.txt.gz · Last modified: 28 Apr 2022 21:36 by David Smith

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