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AD9208-DUAL-EBZ HDL reference design

Functional Overview

The AD9208-DUAL-EBZ reference design is a processor based (e.g. Microblaze) embedded system. The device interfaces to the FPGA transceivers followed by the individual JESD204B and ADC cores. The cores are programmable through an AXI-Lite interface. The samples are passed to the system memory (DDR).

The reference design supports the following evaluation board:

Hardware	Evaluation Document
DUAL-AD9208	DUAL-AD9208

Supported Carriers

VCU118 FMC+ Slot

Block Diagram

The data path and clock domains are depicted on the below diagram.

The design has two JESD receive chains each having 8 lanes at rate of 15Gbps. The JESD receive chain consists of a physical layer represented by an XCVR module, a link layer represented by an RX JESD LINK module and transport layer represented by a RX JESD TPL module. The links operate in Subclass 1 by using the SYSREF signal to edge align the internal local multiframe clock and to release the received data in the same moment from all lanes. Therefore ensuring that data from all channels is synchronized at the application layer.

Both links operate with the following parameters:

Deframer paramaters: L=8, M=2, F=1, S=2, N’=16
GLBLCLK – 375MHz (Lane Rate/40)
REFCLK – 750MHz (Lane Rate/20)
SYSREF – 1.46MHz (DEVCLK/2048)
JESD204B Lane Rate – 15Gbps

Both transport layer components present on their output 256 bits at once, representing 16 samples per link or 8 samples per channel.

The two channels from each converter are merged together and transferred to the DDR with a single DMA. An ADC buffer is used to store 65k samples per channel in the fabric before transferring it with the DMA.

Clock sources

The global clock (LaneRate/40) it is received directly from the clockchip SCLKOUT9 output through the REFCLK1.

Support

Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the EngineerZone.