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resources:eval:user-guides:ad9208_dual_ebz:ad9208_dual_ebz_hdl [10 May 2019 10:08] – [Block Diagram] Laszlo Nagy | resources:eval:user-guides:ad9208_dual_ebz:ad9208_dual_ebz_hdl [26 Apr 2021 16:38] (current) – [More Information] Laszlo Nagy | ||
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==== Functional Overview ==== | ==== Functional Overview ==== | ||
The AD9208-DUAL-EBZ reference design is a processor based (e.g. Microblaze) embedded system. The device interfaces to the FPGA transceivers followed by the individual JESD204B and ADC cores. The cores are programmable through an AXI-Lite interface. The samples are passed to the system memory (DDR). | The AD9208-DUAL-EBZ reference design is a processor based (e.g. Microblaze) embedded system. The device interfaces to the FPGA transceivers followed by the individual JESD204B and ADC cores. The cores are programmable through an AXI-Lite interface. The samples are passed to the system memory (DDR). | ||
+ | |||
+ | <WRAP center round download> | ||
+ | https:// | ||
+ | </ | ||
+ | |||
The reference design supports the following evaluation board: | The reference design supports the following evaluation board: | ||
^Hardware ^Evaluation Document ^ | ^Hardware ^Evaluation Document ^ | ||
- | |[[adi>dual-AD9208|DUAL-AD9208]] | + | |[[adi> |
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* [[xilinx> | * [[xilinx> | ||
+ | |||
+ | ==== Building the HDL project ==== | ||
+ | General build instructions can be found here: [[resources: | ||
==== Block Diagram ==== | ==== Block Diagram ==== | ||
- | The data path and clock domains are depicted on the below diagram. | + | The data path and clock domains are depicted on the below diagram: |
{{ : | {{ : | ||
- | The design has two JESD receive chains each having 8 lanes and operate in subclass 1. | + | The design has two JESD receive chains each having 8 lanes at rate of 15Gbps. |
- | Both links operate | + | The JESD receive chain consists of a physical layer represented by an XCVR module, a link layer represented by an RX JESD LINK module |
- | L=8, M=2, F=1, S=2, N’=16 | + | The links operate |
- | GLBLCLK – 375MHz (Lane Rate/40) | + | Both links are set for full bandwidth mode and operate with the following parameters: |
- | REFCLK – 750MHz (Lane Rate/20) | + | * Deframer paramaters: L=8, M=2, F=1, S=2, N’=16 |
- | SYSREF – 1.46MHz (DEVCLK/ | + | * GLBLCLK – 375MHz (Lane Rate/40) |
- | JESD204B Lane Rate – 15Gbps | + | |
+ | | ||
+ | * DEVCLK – 3000MHz | ||
+ | * JESD204B Lane Rate – 15Gbps | ||
+ | |||
+ | Both transport layer components present on their output 256 bits at once on every clock cycle, representing 8 samples per converter. | ||
+ | The two receive chains are merged together and transferred to the DDR with a single DMA. | ||
+ | An ADC buffer is used to store 65k samples per converter in the fabric before transferring it with the DMA. | ||
=== Clock sources === | === Clock sources === | ||
+ | The clock sources are depicted on the below diagram: | ||
+ | |||
{{ : | {{ : | ||
+ | |||
+ | Both physical layer transceiver modules receive the same reference clock from the clock chip SCLKOUT8 output. | ||
+ | The global clock (LaneRate/ | ||
+ | |||
+ | ==== More Information ==== | ||
+ | * [[: | ||
+ | * [[: | ||
+ | * [[: | ||
+ | * [[: | ||
+ | * [[: | ||
==== Support ==== | ==== Support ==== | ||
- | Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[https://ez.analog.com/ | + | Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[ez>community/ |