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resources:eval:user-guides:ad738x [30 Sep 2019 12:35] – [HDL Design Description] Stanca-Florina Popresources:eval:user-guides:ad738x [13 Jun 2022 14:49] (current) – [No-OS Downloads] Michael Hennerich
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   * [[adi>AD7380]]   * [[adi>AD7380]]
   * [[adi>AD7381]]   * [[adi>AD7381]]
 +  * [[adi>AD7383]]
 +  * [[adi>AD7384]]
 +  * [[adi>AD7386]]
 +  * [[adi>AD7387]]
 +  * [[adi>AD7388]]
 +  * [[adi>AD4680]]
 +  * [[adi>AD4681]]
 +  * [[adi>AD4682]]
 +  * [[adi>AD4683]]
 +  * [[adi>AD4684]]
 +  * [[adi>AD4685]]
  
  
 ===== Evaluation Boards ===== ===== Evaluation Boards =====
-  * [[adi>EVAL-AD738xFMCZ]]+  * [[adi>EVAL-AD7380FMCZ]] 
 +  * [[adi>EVAL-AD7381FMCZ]] 
 +  * [[adi>EVAL-AD7386FMCZ]] 
 +  * [[adi>EVAL-AD7383FMCZ]] 
 +  * [[adi>EVAL-AD7380-4FMCZ]]
    
 ===== Overview ===== ===== Overview =====
-The [[adi>AD7380]] and [[adi>AD7381]] are a 16-bit, 14-bit and 12- +The AD7380 family of generics are dual and quad 16-bit, 14-bit, and 12-bit pin-compatible family of simultaneous sampling, high speed, low power, successive approximation analog-to-digital converters (ADC) that operate from a 3.3 V power supply and features throughput rates up to 4 MSPS. The analog input type is differential for the [[adi>AD7380]], [[adi>AD7381]], [[adi>AD4680]], [[adi>AD4681]], [[adi>AD7380-4]], [[adi>AD7389-4]], [[adi>AD7381-4]]  can accept a wide common mode input voltage, and are sampled and converted on the falling edge of CS. The [[adi>AD7383]], [[adi>AD7384]], [[adi>AD4682]] and [[adi>AD4683]] have the pseudo-differential input while the [[adi>AD7386]], [[adi>AD7387]], [[adi>AD7388]], [[adi>AD4684]] and [[adi>AD4685]]  have single-ended input. The AD7380 family has optional integrated on-chip oversampling blocks to improve dynamic range and reduce noise at lower bandwidths. An internal 2.5 V reference is included.
-bit pin compatible family of dual simultaneous sampling, high +
-speed, low power, successive approximation analog-to-digital +
-converters (ADC) that operate from a 3.3 V power supply and +
-features throughput rates up to 4 MSPS for the [[adi>AD7380]] and  +
-[[adi>AD7381]]. The analog input type is +
-differential, accept a wide common mode input voltage and are +
-sampled and converted on the falling edge of CS.+
  
-The [[adi>AD738x]] has optional integrated on-chip oversampling +Alternatively, an external reference up to 3.3 V can be used. The conversion process and data acquisition use standard control inputs allowing for easy interfacing to microprocessors or DSPs. It is compatible with 1.8 V, 2.5 V, and 3.3 V interfaces, using a separate logic supply.
-blocks to improve dynamic range and reduce noise at lower +
-bandwidths. An internal 2.5 V reference is included.+
  
-Alternatively, an external reference up to 3.3 V can be used. +The dual [[adi>AD7380]], [[adi>AD7381]], [[adi>AD4680]], [[adi>AD4681]], [[adi>AD7383]],[[adi>AD7384]], [[adi>AD4682]], [[adi>AD4683]], [[adi>AD7386]], [[adi>AD7387]], [[adi>AD7388]], [[adi>AD4684]]  and [[adi>AD4685]] family are available in a 16-lead 3mm x 3mm LFCSP package while the quad generics [[adi>AD7380-4]], [[adi>AD7389-4]], and [[adi>AD7381-4]] are available in 4mmx4mm LFCSP package. Both the duals and quad generic operate in specified from −40°C to +125°C temperature range.
-The conversion process and data acquisition use standard +
-control inputs allowing for easy interfacing to microprocessors +
-or DSPs. It is compatible with 1.8 V, 2.5 V, 3.3 V interfaces, +
-using the separate logic supply. +
- +
-The [[adi>AD738x]] is available in a 16-lead LFCSP package with +
-operation specified from −40°C to +125°C.+
  
 ==== Applications ==== ==== Applications ====
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 In the [[:resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] can be found an in-depth presentation and instructions about the HDL design in general. In the [[:resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] can be found an in-depth presentation and instructions about the HDL design in general.
  
-The reference design uses the standard [[https://wiki.analog.com/resources/fpga/peripherals/spi_engine|SPI Engine Framework]] with an integrated pulse generator, which will provide the required conversion rate for the ADC.+The reference design uses the standard [[/resources/fpga/peripherals/spi_engine|SPI Engine Framework]] with an integrated pulse generator, which will provide the required conversion rate for the ADC.
  
 In order to build the HDL design the user has to go through the following steps: In order to build the HDL design the user has to go through the following steps:
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 In order to perform the software setup the user has to go through the following steps: In order to perform the software setup the user has to go through the following steps:
   - Confirm that you have the right tools (the reference design requires XSDK)   - Confirm that you have the right tools (the reference design requires XSDK)
-  - Clone the No-OS GitHub repository (the project is located at [[https://github.com/analogdevicesinc/no-OS/tree/master/ad738x-fmcz|ad738x-fmcz]] ) +  - Clone the No-OS GitHub repository (the project is located at [[https://github.com/analogdevicesinc/no-OS/tree/master/projects/ad738x_fmcz|ad738x-fmcz]] ) 
-  - Follow the instructions provided by [[https://wiki.analog.com/resources/fpga/xilinx/software_setup|software_setup]].+  - Follow the instructions provided by [[/resources/fpga/xilinx/software_setup|software_setup]].
  
 ===== No-OS Driver Description ===== ===== No-OS Driver Description =====
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 ===== No-OS Downloads ===== ===== No-OS Downloads =====
 <WRAP round download 50%> <WRAP round download 50%>
-  * {{https://github.com/analogdevicesinc/no-OS/tree/master/ad738x-fmcz| ad738x No-OS Project.}}+  * [[repo>no-OS/tree/master/projects/ad738x_fmcz | ad738x No-OS Project]]
 </WRAP> </WRAP>
resources/eval/user-guides/ad738x.1569839720.txt.gz · Last modified: 30 Sep 2019 12:35 by Stanca-Florina Pop

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