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--- resources:eval:user-guides:ad713x:hdl [11 Feb 2022 15:29] – [Overview] sergiu arpadi
+++ resources:eval:user-guides:ad713x:hdl [11 Feb 2022 16:52] – fix bd sergiu arpadi
@@ Line 36: / Line 36: @@
 The design only supports the slave mode for both devices with both DCLK and ODR generated by the FPGA. Each device sends data on 4 of the 8 DIN bits.
-{{:resources:fpga:docs:ad713x_hdl_1.svg|spi engine block diagram}}
+{{:resources:fpga:docs:ad713x_hdl_2.svg|spi engine block diagram}}
 In order to build the HDL design the user has to go through the following steps:

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