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| resources:eval:user-guides:ad463x:hdl [17 May 2022 16:24] – [HDL Design Description] Jim Catt | resources:eval:user-guides:ad463x:hdl [29 Jul 2022 09:56] – added AD4630-16 content Padraic O Reilly | ||
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| The HDL reference design for the EVAL-AD4630_FMCZ and EVAL-AD4030_FMCZ provides all the interfaces that are necessary to interact with the device using a Xilinx FPGA development board. | The HDL reference design for the EVAL-AD4630_FMCZ and EVAL-AD4030_FMCZ provides all the interfaces that are necessary to interact with the device using a Xilinx FPGA development board. | ||
| - | The design has all the necessary infrastructure to acquire data from the AD4630-24 24-bit dual-channel precision SAR ADC and AD4030-24 single channel ADC, supporting continuous data capture at maximum 2 MSPS data rate. The design targeted to the Zedboard, which is a low cost FPGA carrier board from Digilent, using a Zynq-7000 re-programmable SoC from Xilinx. | + | The design has all the necessary infrastructure to acquire data from the AD4630-24 24-bit dual-channel precision SAR ADC, AD4630-16 16-bit dual channel precision SAR ADC and AD4030-24 single channel ADC, supporting continuous data capture at maximum 2 MSPS data rate. The design targeted to the Zedboard, which is a low cost FPGA carrier board from Digilent, using a Zynq-7000 re-programmable SoC from Xilinx. |
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| * [[ADI> | * [[ADI> | ||
| + | * [[ADI> | ||
| * [[ADI> | * [[ADI> | ||
| ==== Evaluation board ==== | ==== Evaluation board ==== | ||
| * [[adi> | * [[adi> | ||
| + | * [[adi> | ||
| * [[adi> | * [[adi> | ||
| ==== Supported FPGA carrier ==== | ==== Supported FPGA carrier ==== | ||
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| - | There are three modes in which the system can run. Refer to the [[adi> | + | There are three modes in which the system can run. Refer to the [[adi> |
| === SPI mode - transfer zone 1 === | === SPI mode - transfer zone 1 === | ||
resources/eval/user-guides/ad463x/hdl.txt · Last modified: 15 Mar 2024 17:27 by Michael Bradley