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| resources:eval:user-guides:ad-fmcomms5-ebz:multi-chip-sync [17 Jun 2016 15:52] – [When it's needed to go through a MCS sequence] Robin Getz | resources:eval:user-guides:ad-fmcomms5-ebz:multi-chip-sync [15 May 2017 18:39] – Lars-Peter Clausen | ||
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| ====== Multi-Chip Sync (MCS) ====== | ====== Multi-Chip Sync (MCS) ====== | ||
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| The figure shows a simplified block diagram of the AD9361. The device utilizes a fractional-N synthesizer in the baseband PLL block to generate the desired sample rate for a given system. This synthesizer generates the ADC sample clock, DAC sample clock, and baseband digital clocks from any reference clock in the frequency range specified for the reference clock input. | The figure shows a simplified block diagram of the AD9361. The device utilizes a fractional-N synthesizer in the baseband PLL block to generate the desired sample rate for a given system. This synthesizer generates the ADC sample clock, DAC sample clock, and baseband digital clocks from any reference clock in the frequency range specified for the reference clock input. | ||
resources/eval/user-guides/ad-fmcomms5-ebz/multi-chip-sync.txt · Last modified: 09 Aug 2021 10:04 by Solomon Tan