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— | resources:eval:user-guides:ad-fmcomms5-ebz:multi-chip-sync [05 Feb 2021 15:38] – [No-OS] Michael Hennerich | ||
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+ | ====== Synchronizing multiple AD9361 devices ====== | ||
+ | ====== Overview ====== | ||
+ | |||
+ | Some systems may require more complex configurations that combine multiple devices. Operating multiple [[../ | ||
+ | |||
+ | The AD9361 contains the external control inputs and internal circuitry needed to synchronize baseband sampling and data clocks, allowing the system design to utilize multiple devices in parallel with equivalent performance to a single device. | ||
+ | |||
+ | Unfortunately, | ||
+ | |||
+ | ====== Multi-Chip Sync (MCS) ====== | ||
+ | |||
+ | {{: | ||
+ | |||
+ | The figure shows a simplified block diagram of the AD9361. The device utilizes a fractional-N synthesizer in the baseband PLL block to generate the desired sample rate for a given system. This synthesizer generates the ADC sample clock, DAC sample clock, and baseband digital clocks from any reference clock in the frequency range specified for the reference clock input. | ||
+ | |||
+ | For MIMO systems requiring more than two input or two output channels, multiple AD9361 devices and a common reference oscillator are required. The AD9361 provides the capability to accept an external reference clock and synchronize operation with other devices using simple control logic. This detail is left off the simplified block diagram above. | ||
+ | |||
+ | Each AD9361 includes its own baseband PLL that generates sampling and data clocks from the reference clock input, so an additional control mechanism is required to synchronize multiple devices. A logical SYNC_IN pulse input is needed to align each device’s data clock with a common reference. Having a quick peek in the schematics of the [[hardware# | ||
+ | * '' | ||
+ | * '' | ||
+ | * '' | ||
+ | The '' | ||
+ | |||
+ | The total number of devices that can be connected in parallel is limited only by the drive capability of the clock and logic signals. Although on the FMCOMMS5, we show 2 devices, this can be extended to n devices. | ||
+ | |||
+ | From a hardware perspective - this is all that is necessary, from a software perspective, | ||
+ | |||
+ | ===== Linux ===== | ||
+ | |||
+ | there is a small AD9361 helper library that helps manages the mcs issues, that is common between all IIO software (the iio-oscilloscope, | ||
+ | |||
+ | [[https:// | ||
+ | |||
+ | Specifically, | ||
+ | |||
+ | Calling the function with the two devices is all that is necessary. You can see it being used in the osc application [[https:// | ||
+ | |||
+ | To install the library on your system, follow the instructions below: | ||
+ | < | ||
+ | > **git clone https:// | ||
+ | > **cd libad9361-iio** | ||
+ | > **cmake ./** | ||
+ | > **make** | ||
+ | > **sudo make install**</ | ||
+ | ===== No-OS ===== | ||
+ | |||
+ | Before initializing the parts using the // | ||
+ | |||
+ | After the parts were initialized, | ||
+ | |||
+ | ===== When it's needed to go through a MCS sequence ===== | ||
+ | |||
+ | Any time that software can effect things that can make the part go out of sequence, it's necessary to repeat these steps. This would be any time changes are made to: | ||
+ | * Baseband PLL (BBPLL) rate (device data rates) | ||
+ | * FIR Filter Enable/ | ||
+ | * Changing either Tx or Rx LO settings | ||
+ | |||
+ | ====== RF Phase difference ====== | ||
+ | |||
+ | As mentioned above, the AD9361 does not include internal RF synchronization internally, and needs a little help. | ||
+ | |||
+ | There are two methods to solve this issue: | ||
+ | - measure the phase difference in the internal LOs, and correct in the FPGA | ||
+ | - use an external LO signal | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ===== Internal LOs + FPGA ===== | ||
+ | |||
+ | In this section, we assume that you have read and understood the math parts of [[../ | ||
+ | |||
+ | The FMCOMMS5 board includes two [[adi> | ||
+ | |||
+ | ^ Output \ Input ^ Device A (Rx1C) ^ Device B (Rx1C) ^ | ||
+ | ^ Device A (Tx1B) ^ **1** | **2** | | ||
+ | ^ Device B (Tx1B) ^ **3** | **4** | | ||
+ | |||
+ | controlled by 2 different GPIO pins from the FPGA ('' | ||
+ | |||
+ | {{: | ||
+ | |||
+ | We can use this to find the phase difference the in two difference receivers (A and B) (< | ||
+ | |||
+ | < | ||
+ | |||
+ | Since our minimal switch matrix doesn' | ||
+ | |||
+ | < | ||
+ | |||
+ | Simple algebraic rearranging, | ||
+ | |||
+ | < | ||
+ | |||
+ | The transmitter is the same - by using a common receiver, comparing two transmit paths is quite easy. | ||
+ | |||
+ | < | ||
+ | |||
+ | To measure < | ||
+ | |||
+ | In reality, we should just be able to measure the difference, and set the other difference to the same, but we find it visually appealing to drive all the differences to zero. This is done at the application level - for the osc application, | ||
+ | |||
+ | If you have questions about the code - please [[ez> | ||
+ | |||
+ | ===== When it's needed to go through a internal LO phase calibration sequence ===== | ||
+ | |||
+ | Any time that software can effect things that can make the RF LOs to go out of phase, it's necessary to repeat these steps. This would be any time changes are made to: | ||
+ | * To the internal RX/TX RFPLLs (LOs) | ||
+ | * The MCS is done | ||
+ | |||
+ | This changes does include internal changes, like if you place the AD9361 into TDD mode (where the LOs or LO dividers get powered off). What this really means - is you can't use the AD9361 in TDD mode (where the LOs get turned off) and get phase coherency at the RF level. Users are suggested to keep the LOs on, by using FDD mode. | ||
+ | ===== External LO generation ===== |