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resources:eval:user-guides:ad-fmcomms2-ebz:reference_hdl [24 Sep 2014 21:46] – [Control and SPI] rejeesh kutty | resources:eval:user-guides:ad-fmcomms2-ebz:reference_hdl [09 Jan 2021 00:32] – user interwiki links Robin Getz | ||
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- | ====== | + | |
===== Functional Overview ===== | ===== Functional Overview ===== | ||
- | The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given below. The device interface is a self-contained peripheral similar to other such pcores in the system. The core is programmable through an AXI-lite interface. The data path consists of a VDMA and DMA interface for the transmit and receive path respectively. | + | The reference design is a processor based (ARM, [[wp> |
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The core supports multiple instances of the same synchronized to a common clock. The ADFMCOMMS5 uses two instances of this core synchronized to a common clock. The data is recovered in each individual clock domain and transfers the data to a single clock domain. The multiple cores must all be using the same clock. | The core supports multiple instances of the same synchronized to a common clock. The ADFMCOMMS5 uses two instances of this core synchronized to a common clock. The data is recovered in each individual clock domain and transfers the data to a single clock domain. The multiple cores must all be using the same clock. | ||
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===== Supported Devices ===== | ===== Supported Devices ===== | ||
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* [[adi> | * [[adi> | ||
* [[adi> | * [[adi> | ||
+ | * [[../ | ||
+ | * [[../ | ||
===== Supported Carriers ===== | ===== Supported Carriers ===== | ||
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These are the supported carriers for the HDL - not the complete package (software and HDL). Typically the software lags behind the HDL, so if you don't see the these listed on the main project page - it is not yet done. | These are the supported carriers for the HDL - not the complete package (software and HDL). Typically the software lags behind the HDL, so if you don't see the these listed on the main project page - it is not yet done. | ||
- | Our recommended plaforms are the Zynq based systems: | + | For the FMCOMMS2, 3, 4 based boards, supported carriers include the Xilinx |
* [[xilinx> | * [[xilinx> | ||
* [[xilinx> | * [[xilinx> | ||
* [[http:// | * [[http:// | ||
- | but it also works on the fabric only solutions (for experts, who have used the zynq based systems in the past). | + | but it also works on the Xilinx |
* [[xilinx> | * [[xilinx> | ||
* [[xilinx> | * [[xilinx> | ||
+ | For Altera SoC based systems and the ARRADIO board, we support [[ : | ||
- | ===== Download ====== | + | * [[https:// |
- | FPGA Reference Designs on GitHub | + | ====== |
+ | {{page>:resources: | ||
- | <WRAP round download 80%> | ||
- | * **Vivado Downloads** | ||
- | * https:// | ||
- | |||
- | |||
- | * **XPS/EDK Downloads** | ||
- | * https:// | ||
- | * https:// | ||
- | |||
- | * **Previous Releases & Tags** | ||
- | * https:// | ||
- | * https:// | ||
- | |||
- | * **Git Repository** | ||
- | * https:// | ||
- | </ | ||
<WRAP round help 80%> | <WRAP round help 80%> | ||
- | * Questions? [[http://ez.analog.com/post!input.jspa? | + | * Questions? [[/resources/eval/user-guides/ |
</ | </ | ||
===== Generating Xilinx netlist files ====== | ===== Generating Xilinx netlist files ====== | ||
- | The repository will not contain Xilinx netlist files, only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http:// | + | The repository will not contain Xilinx netlist files, only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/ |
- | {{navigation AD-FMCOMMS2-EBZ# |