The EV-ADF41513SD3Z evaluation board can be used to evaluate all the features and the performance of the ADF41513. The EV-ADF41513 includes an on-board 9.85 GHz to 20.5 GHz ADF5709 VCO. The EV-ADF41513SD3Z board include the ADF41513 frequency synthesizer, 100 MHz reference (crystal oscillator (XO)), loop filter, universal serial bus (USB) interface, low noise LT3045/LT3042 voltage regulators, and a USB cable to connect the board to a PC USB port. For easy programming of the synthesizer, download the Windows®-based software from the ADF41513 product page at www.analog.com/ADF41513. The evaluation board requires a SDP-S, which is not included with the kit. The SDP-S allows software programming of the ADF41513 device through a USB interface. Consult the ADF41513 data sheet in conjunction with this user guide when working with the evaluation boards.
Download the EV-ADF41513SD3Z control software from the ADF41513 product page at www.analog.com/ADF41513. For the software installation procedure, see the PLL Software Installation Guide UG-476.
The EV-ADF41513SD1Z and EV-AD41513SD2Z require the SDP-S platform that uses the EVAL-SDP-CS1Z. Use of SDP-B is not recommended. The evaluation board schematics, assembly, silkscreen, and bill of materials are available in the Evaluation Board Schematics and Artwork section and Ordering Information section. The Gerber fabrication files are available on the ADF41513 product pages on analog.com.
To run the software, perform the following steps:
Under File, the current settings can be saved to or loaded from a text file.
Figure 1. Software Front Panel Display, Select Device and Connection Tab
The board is powered by a 5.5 V (300 mA) power supply connected to the red and black banana connectors. Connect the red connector to a 5.5 V power supply and the black connector to ground. Connect a 25 V (20 mA) power supply to either the V+SMA SMA connector or the test point labeled V+. These connectors power the loop filter op amp. By default, two LDO regulators provide power. The EV-ADF41513SD3Z includes a dedicated 5 V LDO powering the ADF5709 VCO.
The loop filter component placement is shown in Figure 2. The full loop filter can be found in the schematic. For the best in-band phase noise at 15 GHz, use the following components with a 2.4 mA charge pump current and narrow antibacklash pulse (ABP) setting.
Narrower loop filter bandwidths have lower spurious signals.
Figure 2. Loop Filter Placement
The evaluation board contains a 100 MHz single-ended output 5 mm x 7.5 mm XO from Crystek Corporation. The reference source at Y1/Y2 is dual footprint which allows the use of both 5 mm x 7.5 mm and 9 mm x 14 mm XO packages if they are pin compatible. The default 100 MHz XO uses a 3.3 V supply but a 5 V supply XO can be powered from the 5 V LDO by removing R31 and populating R29 with 0 Ω. When using an external reference, remove R8 to disconnect the XO stub and remove R20 to power down the XO. Connect the external reference to the SMA connector labeled REFIN.
All components necessary for local oscillator (LO) generation are inserted on the EV-ADF41513SD3Z board. The board is shipped with the ADF41513 synthesizer, ADF41513 VCO, 100 MHz reference XO, and a 416 kHz loop filter (assuming charge pump current (ICP) = 2.4 mA and RF VCO frequency (RFOUT) = 15 GHz).
The Main Controls tab (see Figure 3) selects the RF and user configurable register settings. Consult the register descriptions of the ADF41513 data sheet for details. The default setting is recommended for most registers. In the RF Settings area, ensure that the VCOout (MHz) box equals the VCO frequency fed back to the PLL. Ensure that the value in the Reference freq. box equals the applied reference signal. The phase frequency detector (PFD) frequency is calculated from the reference frequency, the R counter, the reference doubler, and the reference divide by 2. Ensure that the value in the PFD (MHz) box matches the value specified in the loop filter design. In the Register 5 area, select the value in the CP Current drop down box that matches the value used for the loop filter design.
Figure 3. Software Front Panel Display, Main Controls Tab
To evaluate and test the performance of the EV-ADF41513SD3Z, use the following procedure:
Figure 4 shows a phase noise plot of the SMA RFOUT at 15 GHz.
Figure 4. Single Sideband Phase Noise