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| resources:eval:dpg:eval-ad9148 [26 May 2022 08:37] – Deferson Romero | resources:eval:dpg:eval-ad9148 [10 Aug 2022 04:28] – [Helpful Files:] Melissa Lorenz Lacanlale |
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| =====Helpful Files:===== | =====Helpful Files:===== |
| * User Guide [[adi>media/en/technical-documentation/user-guides/ad9148-ebz-m5375-ebz-ug-1631.pdf|UG-1631]] | * User Guide for DPG3 users:[[adi>media/en/technical-documentation/user-guides/ad9148-ebz-m5375-ebz-ug-1631.pdf|UG-1631]] |
| * Datasheet [[adi>media/en/technical-documentation/data-sheets/AD9148.pdf|AD9148]] | * Datasheet [[adi>media/en/technical-documentation/data-sheets/AD9148.pdf|AD9148]] |
| * IBIS Model [[adi>en/license/ibis-models?mediaPath=media/en/simulation-models/ibis-models/ad9148.ibs&modelType=ibis-models|AD9148]] | * IBIS Model [[adi>en/license/ibis-models?mediaPath=media/en/simulation-models/ibis-models/ad9148.ibs&modelType=ibis-models|AD9148]] |
| =====Quick Start Guide===== | =====Quick Start Guide===== |
| ====Reconfiguring the Evaluation Board==== | ====Reconfiguring the Evaluation Board==== |
| This section details the quick start procedures for setting up the AD9740-FMC-EBZ/AD9742-FMC-EBZ/AD9744-FMC-EBZ/ AD9748-FMC-EBZ evaluation board. Refer to the table below to configure the power supply and the Reference & synchronization clock. | This section details the quick start procedures for setting up the AD9148-EBZ & AD9148-M5375-EBZ evaluation board. Refer to the section below to configure the power supply and the Reference & synchronization clock. |
| ====Power Supply Configuration==== | ====Power Supply Configuration==== |
| The evaluation board has a provision for on board or external power supply configuration. | The evaluation board has a provision for on board or external power supply configuration. |
| ===Internal Power Supply=== | ===Internal Power Supply=== |
| On board power supply is implemented by default. | On board power supply is implemented by default. |
| The **JP1** selects the supply voltage level for IOVDD. Refer to Figure 2. | **JP1** selects the supply voltage level for IOVDD. Refer to Figure 2. |
| * When Pin 1 and Pin 2 are connected, IOVDD = 3.3 V (Default) | * When Pin 1 and Pin 2 are connected, IOVDD = 3.3 V (Default) |
| * When Pin 2 and Pin 3 are connected, IOVDD = 1.8 V <WRAP centeralign>{{:resources:eval:dpg:ad9148-ebz-jp1_pin_1.png?350x350}}{{:resources:eval:dpg:ad9148-m5375-ebz-jp1_pin_2.png?360x360}}</WRAP><WRAP centeralign>//Figure 2. AD9148-EBZ JP1/AD9148-M5375-EBZ JP1//</WRAP> | * When Pin 2 and Pin 3 are connected, IOVDD = 1.8 V <WRAP centeralign>{{:resources:eval:dpg:ad9148-ebz-jp1_pin_1.png?350x350}}{{:resources:eval:dpg:ad9148-m5375-ebz-jp1_pin_2.png?360x360}}</WRAP><WRAP centeralign>//Figure 2. AD9148-EBZ JP1/AD9148-M5375-EBZ JP1//</WRAP> |
| To implement external supply configuration, remove the header shunt of six pin jumpers, as shown in Figure 3. Refer to Table 1 for external supply jumper connection.<WRAP centeralign>{{:resources:eval:dpg:ad9148-ebz_pinjumpers_1.png?350x350}}{{:resources:eval:dpg:ad9148-m5375-ebz-pinjuumpers_2.png?380x380}}</WRAP><WRAP centeralign>//Figure 3. AD9148-EBZ/AD9148-M5375-EBZ Pin Jumpers//</WRAP><WRAP centeralign>{{ :resources:eval:dpg:table1.jpg?800 |}}//Table 1. AD9148-EBZ/AD9148-M5375-EBZ Jumper Connection//</WRAP> | To implement external supply configuration, remove the header shunt of six pin jumpers, as shown in Figure 3. Refer to Table 1 for external supply jumper connection.<WRAP centeralign>{{:resources:eval:dpg:ad9148-ebz_pinjumpers_1.png?350x350}}{{:resources:eval:dpg:ad9148-m5375-ebz-pinjuumpers_2.png?380x380}}</WRAP><WRAP centeralign>//Figure 3. AD9148-EBZ/AD9148-M5375-EBZ Pin Jumpers//</WRAP><WRAP centeralign>{{ :resources:eval:dpg:table1.jpg?800 |}}//Table 1. AD9148-EBZ/AD9148-M5375-EBZ Jumper Connection//</WRAP> |
| ====Reference and Synchronization Clock==== | ====Reference and Synchronization Clock==== |
| JP15 and JP18 selects the source for the reference and synchronization clock of the AD9148. the on board clocking is implemented by default. Refer to figure # to reconfigure the reference/ synchronization clock. | JP15 and JP18 selects the source for the reference and synchronization clock of the AD9148. the on board clocking is implemented by default. Refer to figure #4 to reconfigure the reference/ synchronization clock. |
| * On board (from AD9516), center pads connected to inner pad. | * On board (from AD9516), center pads connected to inner pad. |
| * Off board (External source), center pads connected to outer pad.<WRAP centeralign>{{ :resources:eval:dpg:ad9148_clockref.png?800 |}}//Figure 4. AD9148-EBZ/AD9148-M5375-EBZ Clock Source Configuration//</WRAP> | * Off board (External source), center pads connected to outer pad.<WRAP centeralign>{{ :resources:eval:dpg:ad9148_clockref.png?800 |}}//Figure 4. AD9148-EBZ/AD9148-M5375-EBZ Clock Source Configuration//</WRAP> |
| * Set clock input to 400MHz and 3dBm. | * Set clock input to 400MHz and 3dBm. |
| - Open the SPI software from Start > Programs > Analog Devices < 9148 > AD9148 SPI. | - Open the SPI software from Start > Programs > Analog Devices < 9148 > AD9148 SPI. |
| - Click update AD9516 then run, refer to Figure 5. <WRAP centeralign>{{ :resources:eval:dpg:ad9148-spi-run.png?600 |}}//Figure 5. Running ACE Initial Configuration Wizard when using SDP-H1//</WRAP> | - With the default settings, click run. The update AD9516 should blink, refer to Figure 5. <WRAP centeralign>{{ :resources:eval:dpg:ad9148-spi-run.png?600 |}}//Figure 5. Running ACE Initial Configuration Wizard when using SDP-H1//</WRAP> |
| - Open the DPGDownloader software from Start >Programs > Analog Devices > DPG > DPGDownloader. The DPG downloader should detect the AD9148 Evaluation board as well as the DCO Frequency. | - Open the DPGDownloader software from Start >Programs > Analog Devices > DPG > DPGDownloader. The DPG downloader should detect the AD9148 Evaluation board as well as the DCO Frequency. |
| - From DPGDownloader, Add Generator Waveforms pulldown menu select Single Tone and apply the settings as shown in Figure 6. Set the Data Rate to 100MHz and frequency to 15 MHz. Set DAC resolution to the DAC’s number of bits to 16. Check the "Generate Complex Data (I & Q)" box then uncheck the “Unsigned Data” box. | - From DPGDownloader, Add Generator Waveforms pulldown menu select Single Tone and apply the settings as shown in Figure 6. Set the Data Rate to 100MHz and frequency to 15 MHz. Set DAC resolution to the DAC’s number of bits to 16. Check the "Generate Complex Data (I & Q)" box then uncheck the “Unsigned Data” box. |
| - Select the in-phase tone from the I Data Vector pulldown menu and the quadrature tone from the Q Data Vector pulldown menu.<WRAP centeralign>{{ :resources:eval:dpg:ad9148-dpgdownloader.png |}}//Figure 6. DPGDownloader Waveform Configuration for AD9148-EBZ//</WRAP> | - Select the in-phase tone from the I Data Vector pulldown menu and the quadrature tone from the Q Data Vector pulldown menu.<WRAP centeralign>{{ :resources:eval:dpg:ad9148-dpgdownloader.png |}}//Figure 6. DPGDownloader Waveform Configuration for AD9148-EBZ//</WRAP> |
| - Press the download arrow and then the play button. The spectrum similar to Figure 7 should appear in the signal/spectrum analyzer. <WRAP centeralign>{{ :resources:eval:dpg:microsoftteams-image_5_.png?600 |}}//Figure 7. AD9148-EBZ FFT for Fdac=200MHz, Fout=14.91MHz//</WRAP> | - Press the download arrow and then the play button. The spectrum similar to Figure 7 should appear in the signal/spectrum analyzer. <WRAP centeralign>{{ :resources:eval:dpg:microsoftteams-image_5_.png?600 |}}//Figure 7. AD9148-EBZ FFT for Fdac=400MHz,4x Interpolation Fout=15MHz//</WRAP> |
