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| resources:eval:dpg:eval-ad9146 [28 Jan 2012 00:31] – Approved Jason Coutermarsh | resources:eval:dpg:eval-ad9146 [16 Jun 2023 05:53] (current) – John Marco Mina | ||
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| - | ======AD9146 | + | ======EVALUATING THE AD9146 |
| - | Documentation and software updates for using the [[adi> | + | =====Preface===== |
| - | =====Files included in the AD9146 Update:===== | + | This user guide describes both the hardware and software setup needed to acquire data capture from [[adi>eval-ad9146|AD9146-M5375-EBZ]] |
| - | * SPI Application | + | |
| - | * DPGDownloader Panel | + | |
| - | * [[ftp:// | + | |
| - | * [[adi>static/ | + | |
| - | * [[adi>/ | + | |
| - | * [[ftp:// | + | |
| - | * [[ftp:// | + | |
| - | * [[ftp:// | + | |
| - | * [[ftp:// | + | |
| - | * [[ftp:// | + | |
| - | Download the [[ftp://ftp.analog.com/pub/HSSP_SW/HSCDAC/HSDAC_Update/HSDACUpdate_AD9146_1.0.4392.24346.exe|AD9146 Update]] | + | This guide shows how AD9146-M5375-EBZ works with [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-sdp-h1.html|SDP-H1]] or [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ |
| - | {{section> | + | =====Typical Setup===== |
| + | {{ : | ||
| + | <WRAP centeralign>//Figure 1a. EVAL-AD9146 Setup with SDP-H1//</ | ||
| + | |||
| + | {{ :resources: | ||
| + | <WRAP centeralign>// | ||
| + | |||
| + | <note tip>Tip: Click on any picture in this guide to open an enlarged version.</ | ||
| + | |||
| + | =====Helpful Files: | ||
| + | * {{ : | ||
| + | * Data Sheet: [[adi> | ||
| + | * IBIS Model: [[adi>/ | ||
| + | * Schematic: {{ : | ||
| + | * Bill of Materials: {{ : | ||
| + | * PCB Gerber files: {{ : | ||
| + | * PCB BRD file: {{ : | ||
| + | * PCB Layout PDF: {{ : | ||
| + | |||
| + | =====Software Needed: | ||
| + | * [[: | ||
| + | * [[: | ||
| + | < | ||
| + | |||
| + | =====Hardware Needed: | ||
| + | * [[adi> | ||
| + | * [[: | ||
| + | * [[adi> | ||
| + | * 5Vdc 2A Power Supply | ||
| + | * PC with ACE and DPG Lite Software Applications | ||
| + | * High-Frequency Continuous Wave Generator | ||
| + | * Signal/ | ||
| + | * USB-A to USB-Mini Cable | ||
| + | * (2) SMA Cables | ||
| + | * The following are included in SDP-H1 Evaluation Kit: | ||
| + | * 12Vdc 2.5A Wall Wart | ||
| + | * USB-A to USB-Mini Cable | ||
| + | * The following are included in ADS7-V2 Evaluation Kit: | ||
| + | * 12V 60W AC/DC Power Supply | ||
| + | * Power Cord | ||
| + | * USB-A to USB-B Cable | ||
| + | |||
| + | =====Quick Start Guide===== | ||
| + | - Make sure that on the evaluation board, JP4, JP5, JP6, and JP7 are configured such that I and Q outputs are connected to the corresponding baluns (T7, T8). Refer to Figure 6. Configure JP10 and JP15 such that AD9146 clock input is connected to AD9516 clock divider/ | ||
| + | - Attach the evaluation board to the FMC connector of SDP-H1 or ADS7-V2 using the AD-DAC-FMC-ADP adapter board. Connect continuous wave generator for clock input to J1, and the DAC output from J5 or J9 to a signal/ | ||
| + | * If using **SDP-H1**, set clock input to **100 MHz and 0 dBm**. Connect SDP-H1 to PC via USB and to a 12Vdc wall wart. | ||
| + | * If using **ADS7-V2**, | ||
| + | - Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9146 evaluation board. Apply the configuration wizard settings shown in Figure 2a for SDP-H1 and in Figure 2b for ADS7-V2. <WRAP centeralign> | ||
| + | * If using **SDP-H1**, set **DAC frequency** to 100 MHz, **Interpolation** to 2x and **Data Format** to binary format. | ||
| + | * If using **ADS7-V2**, | ||
| + | - In ACE, AD9146 on-chip PLL can be enabled or not. To enable the on-chip PLL check the **Enable PLL Clock** in the wizard under **AD9146 PLL Setup**. Select **Auto Mode** for PLL Mode option. The **PLL Locked** LED on the ACE Board View should light up green. If the LED doesn' | ||
| + | - Start DPG Lite or DPG Downloader. | ||
| + | * At the SDP-H1 part of the software, the device part number and **DCO frequency** of around **100 MHz** should be displayed. | ||
| + | * At the ADS7-V2 part of the software, the device part number and **DCO frequency** of around **500 MHz** should be displayed. | ||
| + | - In DPG Lite or DPG Downloader, from the **Add Generator | ||
| + | * When using SDP-H1, set **Data Rate** to 50 MHz and **Desired Frequency** to 10 MHz. | ||
| + | * When using ADS7-V2, set **Data Rate** to 250 MHz and **Desired Frequency** to 21 MHz. | ||
| + | - Continuing on setting up DPG Lite or DPG Downloader, set **DAC resolution** to 16 bits. Check off the **Generate Complex Data (I & Q)** box.\\ <WRAP centeralign> | ||
| + | - Select the in-phase tone from the **I Data Vector** pulldown menu and the quadrature tone from the **Q Data Vector** pulldown menu. | ||
| + | - Press the download arrow and then the play button. The FFT plots similar to Figures 4a and 4b should appear in the signal/ | ||
| + | |||
| + | =====Reconfiguring the Evaluation Board===== | ||
| + | |||
| + | ====Jumpers for Selecting the Clock Source==== | ||
| + | |||
| + | The AD9146 has an on-chip phase-locked loop (PLL) that uses the REFCLKP and REFCLKN pins to supply the reference clock. The AD9146-M5375-EBZ can supply the clock either from the AD9516-0 clock chip or from an additional external signal generator by connecting to J14. Connecting the inner pads to JP10 and JP15 selects the option to use the AD9146 by default, whereas soldering the outer pads chooses the external option to drive from a sine source.\\ | ||
| + | |||
| + | <WRAP centeralign> | ||
| + | |||
| + | ====Jumpers for Selecting DAC Output Configuration==== | ||
| + | |||
| + | The AD9146-M5375-EBZ evaluates both the DAC I/Q outputs as well as the modulator RF outputs. Table 1 lists the jumper configurations and the SMA connections needed to view either the DAC IF outputs or the RF outputs on the spectrum analyzer.\\ | ||
| + | {{ : | ||
| + | |||
| + | The evaluation board has four three pad solder jumpers, two for each DAC (IOUT1N and IOUT1P, and IOUT2 N and IOUT2P). Use these solder jumpers, JP4 through JP7, to choose between viewing the DAC output or the modulator output. By default, the jumpers are configured to view the DAC output. For the modulator, solder the inner pads. | ||
| + | |||
| + | <WRAP centeralign> | ||
| + | |||
| + | ====Hardware Provisions for Power Supplies==== | ||
| + | |||
| + | The AD9146-M5375-EBZ has five, two pin jumpers for each of the different power supplies on the board (see Table 2). By default, all of these jumpers must be populated.\\ | ||
| + | {{ : | ||
| + | |||
| + | ====Jumper for Transmit Enable pin==== | ||
| + | |||
| + | The AD9146 has a transmit enable feature (active low) that allows the user to control when the DACs transmit and when the outputs are clamped. This feature can be used by forcing a voltage on the TXENABLE pin via a test point. By default, the TXENABLE pin is set by the controller. Connect JP1 horizontally, | ||
| + | |||
| + | <WRAP centeralign> | ||
resources/eval/dpg/eval-ad9146.1327707075.txt.gz · Last modified: 28 Jan 2012 00:31 by Jason Coutermarsh