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| Both sides previous revisionPrevious revision | Last revisionBoth sides next revision | ||
| resources:eval:dpg:dpg2 [18 Jul 2012 15:13] – Approved Jason Coutermarsh | resources:eval:dpg:dpg2 [07 Aug 2012 14:27] – [Hardware Specifications] Jason Coutermarsh | ||
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| * On-connector clock input for all interfaces | * On-connector clock input for all interfaces | ||
| * Optional external clock input via SMA jack for CMOS interfaces | * Optional external clock input via SMA jack for CMOS interfaces | ||
| + | * Rated for operation only at 25ºC | ||
| * Multi-Unit Synchronization | * Multi-Unit Synchronization | ||
| * Up to four DPG2's may have their LVDS interfaces synchronized together | * Up to four DPG2's may have their LVDS interfaces synchronized together | ||
| * Requires additional Synchronization Board and cabling | * Requires additional Synchronization Board and cabling | ||
| {{: | {{: | ||
| + | | ||
| ====== Output Data ====== | ====== Output Data ====== | ||
| The DPG2 has two 16-bit ports capable of interfacing with both LVDS and LVCMOS devices. When transmitting a data vector each sample from the data file is played sequentially on the output port. Note that while the two data ports are labeled " | The DPG2 has two 16-bit ports capable of interfacing with both LVDS and LVCMOS devices. When transmitting a data vector each sample from the data file is played sequentially on the output port. Note that while the two data ports are labeled " | ||
resources/eval/dpg/dpg2.txt · Last modified: 03 Apr 2014 18:59 by Michael Fowler