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resources:eval:dpg:ad9154-ace-ebz [30 Nov 2015 20:38] – r Larry Welchresources:eval:dpg:ad9154-ace-ebz [30 Nov 2015 21:29] (current) – d Larry Welch
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 The AD9154-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal processing RF Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9154-EBZ via its JESD204B lanes. The Evaluation Board (EVB) runs from a single +5V lab supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a CFRAME clock used by the DPG3.  The AD9154-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal processing RF Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9154-EBZ via its JESD204B lanes. The Evaluation Board (EVB) runs from a single +5V lab supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a CFRAME clock used by the DPG3. 
 ===== AD9154 Evaluation Software ===== ===== AD9154 Evaluation Software =====
-The AD9154 Evaluation Board software runs on the ADI ACE graphical user interface (GUI). ACE is included on the Evaluation board CD.  Registers on the AD9154 and AD9516 products are programmed by the ACE software via a USB cable connecting the user’s PC to the AD9154-EBZ XP2 connector. Software in the AD9154-EBZ PIC processor (XU1) provides  the interface between the USB bus and the SPI busses of the AD9154 and AD9516.  +The AD9154 Evaluation Board software runs on the ADI ACE graphical user interface (GUI). ACE is included on the Evaluation board CD.  Registers on the AD9154 and AD9516 products are programmed by the ACE software via a USB cable connecting the user’s PC to the AD9154-EBZ XP2 connector. Firware in the AD9154-EBZ PIC processor (XU1) provides  the interface between the USB bus and the SPI busses of the AD9154 and AD9516.  
 ===== Hardware Setup ===== ===== Hardware Setup =====
  Figure 1 shows the block diagram of the set-up.    Figure 1 shows the block diagram of the set-up.  
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 {{:resources:eval:dpg:9154ebz_figure_5.png?nolink|}} {{:resources:eval:dpg:9154ebz_figure_5.png?nolink|}}
-|  Figure 5 DPG Downloader Panel at Start Up  |+|  Figure 4 DPG Downloader Panel at Start Up  |
  
  
 {{:resources:eval:dpg:9154ebz_figure_6.png?nolink|}} {{:resources:eval:dpg:9154ebz_figure_6.png?nolink|}}
-|  Figure 6 Fully Configured DPG Downloader Panel  |+|  Figure 5 Fully Configured DPG Downloader Panel  |
  
  
resources/eval/dpg/ad9154-ace-ebz.1448912323.txt.gz · Last modified: 30 Nov 2015 20:38 by Larry Welch

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