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resources:eval:dpg:ad9154-ace-ebz [24 Nov 2015 21:59] – h Larry Welchresources:eval:dpg:ad9154-ace-ebz [30 Nov 2015 21:29] (current) – d Larry Welch
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 The AD9154-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal processing RF Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9154-EBZ via its JESD204B lanes. The Evaluation Board (EVB) runs from a single +5V lab supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a CFRAME clock used by the DPG3.  The AD9154-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal processing RF Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9154-EBZ via its JESD204B lanes. The Evaluation Board (EVB) runs from a single +5V lab supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a CFRAME clock used by the DPG3. 
 ===== AD9154 Evaluation Software ===== ===== AD9154 Evaluation Software =====
-The AD9154 Evaluation Board software runs on the ADI ACE graphical user interface (GUI). ACE is included on the Evaluation board CD.  Registers on the AD9154 and AD9516 products are programmed by the ACE software via a USB cable connecting the user’s PC to the AD9154-EBZ XP2 connector. Software in the AD9154-EBZ PIC processor (XU1) provides  the interface between the USB bus and the SPI busses of the AD9154 and AD9516.  +The AD9154 Evaluation Board software runs on the ADI ACE graphical user interface (GUI). ACE is included on the Evaluation board CD.  Registers on the AD9154 and AD9516 products are programmed by the ACE software via a USB cable connecting the user’s PC to the AD9154-EBZ XP2 connector. Firware in the AD9154-EBZ PIC processor (XU1) provides  the interface between the USB bus and the SPI busses of the AD9154 and AD9516.  
 ===== Hardware Setup ===== ===== Hardware Setup =====
  Figure 1 shows the block diagram of the set-up.    Figure 1 shows the block diagram of the set-up.  
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 1. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1500MHz, and the output level to 3dBm. The spectrum analyzer can be configured as shown in Figure 7 with a resolution bandwidth of 100kHz. Choose an Input Attenuation of 24dB.  1. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1500MHz, and the output level to 3dBm. The spectrum analyzer can be configured as shown in Figure 7 with a resolution bandwidth of 100kHz. Choose an Input Attenuation of 24dB. 
  
-2. On your lab computer, open the AD9154 SPIPro application (Start > All Programs > Analog Devices > AD9154 > AD9154 SPI). You will see the GUI shown in Figure 3 come up. +2. Open ACE from Start->Analog Devices->ACE. ACE will come up and display the initial ACE page shown in figure 3a.  \\ \\ 
- +3. Press the AD9154 icon and populate the AD9154 initialization wizard as shown in figure 3b, JESD mode 0, Interpolation 2. Leave all other settings in their default state. Press rhe APPLY button. JESD204B PLL lock will turn green as shown in figure 3c. Press the AD9154 icon in the initialization wizard tab. The AD9154 block diagram view will appear populated as shown in figure 3d.\\ \\
- +
- +
-{{:resources:eval:dpg:9154ebz_figure_3.png?nolink|}} +
-|    Figure 3. AD9154 SPIPro at start up   | +
- +
- +
-3. Open ACE from Start->Analog Devices->ACE. ACE will come up and display the initial ACE page shown in figure 4a.  \\ \\ +
-4. Press the AD9154 icon and populate the AD9154 initialization wizard as shown in figure 4b, JESD mode 0, Interpolation 2. Leave all other settings in their default state. Press rhe APPLY button. JESD204B PLL lock will turn green as shown in figure 4c. Press the AD9154 icon in the initialization wizard tab. The AD9154 block diagram view will appear populated as shown in figure 4d.\\ \\+
 <WRAP center>  <WRAP center> 
-{{:resources:eval:dpg:9154_fmc_figure6ace.png?nolink|}} +{{:resources:eval:dpg:ace_ad9154_ebz_realinit.png?nolink|}} 
-|  Figure 4a. Initial ACE page for AD9154-FMC-EBZ  | +|  Figure 3a. Initial ACE page for AD9154-FMC-EBZ  | 
-{{:resources:eval:dpg:9154_fmc_figure6bace.png?nolink|}} +{{:resources:eval:dpg:ace_ad9154_ebz_init.png?nolink|}} 
-|  Figure 4b. ACE AD9154 Initialization Wizard tab with selections made  | +|  Figure 3b. ACE AD9154 Initialization Wizard tab with selections made  | 
-{{:resources:eval:dpg:9154_fmc_figure6cace.png?nolink|}} +{{:resources:eval:dpg:ace_ad9154_ebz_afterapply.png?nolink|}} 
-|  Figure 4c. ACE AD9154 Initialization Wizard tab after pressing APPLY  | +|  Figure 3c. ACE AD9154 Initialization Wizard tab after pressing APPLY  | 
-{{:resources:eval:dpg:9154_fmc_figure6dace.png?nolink|}} +{{:resources:eval:dpg:ace_ad9154_ebz_block.png?nolink|}} 
-|  Figure 4d. ACE AD9154 Block Diagram View after Initialization  |+|  Figure 3d. ACE AD9154 Block Diagram View after Initialization  |
 </WRAP> </WRAP>
  
-5. DPGDownloader Start Up Sequence+4. DPGDownloader Start Up Sequence
  
-a. Open DPGDownloader. (Start > All Programs > Analog Devices > DPG > DPGDownloader). DPGDownloader GUI will come up as shown Figure 5.  +a. Open DPGDownloader. (Start > All Programs > Analog Devices > DPG > DPGDownloader). DPGDownloader GUI will come up as shown Figure 4.  
  
 b. Select the Port configuration QBF 1X8 85G 425M. The configuration progress bar will then show a moving green indication. b. Select the Port configuration QBF 1X8 85G 425M. The configuration progress bar will then show a moving green indication.
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 c. Once port configuration is complete, select “add generated waveform” and “single tone”. c. Once port configuration is complete, select “add generated waveform” and “single tone”.
  
-d. Set Data Rate to 750Mhz, Desired Frequency to 182Mhz, Amplitude to -1.0 dBFS, uncheck unsigned, check Generate Complex Data (I&Q).+d. Set Data Rate to 750Mhz, Desired Frequency to 112Mhz, Amplitude to -1.0 dBFS, uncheck unsigned, check Generate Complex Data (I&Q).
  
 e. Under Data Playback, select I data for DAC 0 and DAC2, and Q data for DAC 1 and DAC3. e. Under Data Playback, select I data for DAC 0 and DAC2, and Q data for DAC 1 and DAC3.
  
-f. Click Download then Play. The spectrum in Figure 7 will appear on all 4 DAC outputs (J17, J4, J5, and J7), Serial Line Rate will be 7.5Gbps. Figure 8 is a scope capture of the DAC output signal taken on three of the channels.+f. Click Download then Play. The spectrum in Figure 6 will appear on all 4 DAC outputs (J17, J4, J5, and J7), Serial Line Rate will be 7.5Gbps. Figure 7 is a scope capture of the DAC output signal taken on three of the channels.
  
-6. On SPIPro Quick Start Tab, click “Read All Registers” and confirm the GUI looks the same as Figure 4. +5. On SPIPro Quick Start Tab, click “Read All Registers” and confirm the GUI looks the same as Figure 4. 
  
  
 {{:resources:eval:dpg:9154ebz_figure_5.png?nolink|}} {{:resources:eval:dpg:9154ebz_figure_5.png?nolink|}}
-|  Figure 5 DPG Downloader Panel at Start Up  |+|  Figure 4 DPG Downloader Panel at Start Up  |
  
  
 {{:resources:eval:dpg:9154ebz_figure_6.png?nolink|}} {{:resources:eval:dpg:9154ebz_figure_6.png?nolink|}}
-|  Figure 6 Fully Configured DPG Downloader Panel  |+|  Figure 5 Fully Configured DPG Downloader Panel  |
  
  
  
-8. Here is what you will see at the output of DAC0 on the Spectrum Analyzer. \\ \\+6. Here is what you will see at the output of DAC0 on the Spectrum Analyzer. \\ \\
  
  
 {{:resources:eval:dpg:9154ebz_figure_7.png?nolink|}} {{:resources:eval:dpg:9154ebz_figure_7.png?nolink|}}
  
-|  Figure 7. DAC Output Spectrum Analyzer Display  |+|  Figure 6. DAC Output Spectrum Analyzer Display  |
  
  
-9. Here’s what you will see on DAC1, DAC2, and DAC3 on the scope. +7. Here’s what you will see on DAC1, DAC2, and DAC3 on the scope. 
  
 {{:resources:eval:dpg:9154ebz_figure_8.png?nolink|}} {{:resources:eval:dpg:9154ebz_figure_8.png?nolink|}}
-|  Figure 8. DAC Outputs Scope Display |+|  Figure 7. DAC Outputs Scope Display |
  
resources/eval/dpg/ad9154-ace-ebz.1448398774.txt.gz · Last modified: 24 Nov 2015 21:59 by Larry Welch

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