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resources:eval:dpg:ad9129-cbltx-ebz [14 Sep 2012 15:42] – [Getting Started] Dan Fague | resources:eval:dpg:ad9129-cbltx-ebz [05 Feb 2013 18:28] (current) – Added the AD9119-CBLTX-EBZ Dan Fague | ||
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- | ~~under construction~~ | + | ====== |
- | ====== AD9129-CBLTX-EBZ Cable Transmitter Evaluation Board Quick Start Guide ====== | + | ===== Getting Started with the AD9119/AD9129 Cable Transmitter Evaluation Board and Software ===== |
- | ===== Getting Started with the AD9129 Cable Transmitter Evaluation Board and Software ===== | + | |
==== What's in the Box ==== | ==== What's in the Box ==== | ||
- | * AD9129-CBLTX-EBZ Evaluation Board | + | * AD9119-CBLTX-EBZ or AD9129-CBLTX-EBZ Evaluation Board |
* Mini-USB Cable | * Mini-USB Cable | ||
* Evaluation Board CD | * Evaluation Board CD | ||
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* Data Pattern Generator Series 2 (DPG2) | * Data Pattern Generator Series 2 (DPG2) | ||
* Spectrum Analyzer Ex: Agilent PXA or Rohde Schwarz FSU | * Spectrum Analyzer Ex: Agilent PXA or Rohde Schwarz FSU | ||
- | ==== Introduction ==== | + | ===== Introduction ===== |
- | The AD9129-CBLTX-EBZ connects to a DPG2 to allow for quick evaluation of the AD9129, a high-speed, RF Digital to Analog converter (RF DAC). The DPG2 automatically formats the data and sends it to the AD9129-CBLTX-EBZ, | + | The AD9119-CBLTX-EBZ and AD9129-CBLTX-EBZ are built from the same printed circuit board, with the only difference being which DAC device is loaded, the AD9119 or the AD9129. This Quick Start Guide will describe the set-up of the AD9129-CBLTX-EBZ, |
- | ==== AD9129 Evaluation Software ==== | + | |
+ | The AD9129-CBLTX-EBZ connects to a DPG2 to allow for quick evaluation of the AD9129, a high-speed, RF Digital to Analog converter (RF DAC). The DPG2 automatically formats the data and sends it to the AD9129-CBLTX-EBZ, | ||
+ | ===== AD9129 Evaluation Software | ||
The AD9129 Evaluation Board software has an easy-to-use graphical user interface (GUI). It is included on the Evaluation Board CD, or can be downloaded from the DPG Web site at http:// | The AD9129 Evaluation Board software has an easy-to-use graphical user interface (GUI). It is included on the Evaluation Board CD, or can be downloaded from the DPG Web site at http:// | ||
- | ==== Hardware Setup ==== | + | ===== Hardware Setup ===== |
Connect +5V to P3, GND to P4, and +8V to P5. The evaluation board connects to the DPG2 unit through connectors P1 and P2. The spectrum analyzer should connect to the N-connector at J1. Because cable systems are typically 75 Ω systems, the output of the board is also 75 Ω. For best results using a 50 Ω spectrum analyzer, a transformer should be used to transform the output impedance from 75 Ω to 50 Ω. The PC should be connected to the EVB using the mini-USB connector XP2 after installation of the Evaluation Board software. | Connect +5V to P3, GND to P4, and +8V to P5. The evaluation board connects to the DPG2 unit through connectors P1 and P2. The spectrum analyzer should connect to the N-connector at J1. Because cable systems are typically 75 Ω systems, the output of the board is also 75 Ω. For best results using a 50 Ω spectrum analyzer, a transformer should be used to transform the output impedance from 75 Ω to 50 Ω. The PC should be connected to the EVB using the mini-USB connector XP2 after installation of the Evaluation Board software. | ||
- | < | + | < |
{{: | {{: | ||
</ | </ | ||
- | < | + | < |
{{ : | {{ : | ||
</ | </ | ||
<WRAP clear> | <WRAP clear> | ||
</ | </ | ||
- | < | + | < |
Figure 1 - Block diagram of the AD9129 lab bench set-up | Figure 1 - Block diagram of the AD9129 lab bench set-up | ||
</ | </ | ||
- | < | + | < |
Figure 2 - Top view of AD9129-CBLTX-EBZ Evaluation Board | Figure 2 - Top view of AD9129-CBLTX-EBZ Evaluation Board | ||
</ | </ | ||
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</ | </ | ||
- | ==== Getting Started ==== | + | ===== Getting Started |
The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http:// | The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http:// | ||
The following procedure will set up a basic 1-carrier, 256-QAM signal. | The following procedure will set up a basic 1-carrier, 256-QAM signal. | ||
- | === Initial Set-Up === | + | ==== Initial Set-Up |
- | 1. Install the DPG Downloader, ADF4350, and AD9129 software and support files on your PC | + | 1. Install the DPG Downloader, ADF4350, and AD9129 software and support files on your PC \\ |
- | 2. Start the AD9129 Control Panel GUI (but don’t hit the run arrow yet) | + | 2. Start the AD9129 Control Panel GUI (but don’t hit the run arrow yet) \\ |
- | 3. Connect the EVB to your PC and lab equipment as shown in Figure 1 above. Use a USB cable to connect your PC to the EVB, and another USB cable to connect your PC to the DPG2 unit. Note that a DPG3 unit can also be used. | + | 3. Connect the EVB to your PC and lab equipment as shown in Figure 1 above. Use a USB cable to connect your PC to the EVB, and another USB cable to connect your PC to the DPG2 unit. Note that a DPG3 unit can also be used. \\ |
- | 4. Start the ADF4350 SPI for AD9129 | + | 4. Start the ADF4350 SPI for AD9129 |
It is suggested that the basic set-up is verified before making any modifications to the evaluation board. | It is suggested that the basic set-up is verified before making any modifications to the evaluation board. | ||
- | === Load Initial Settings === | + | ==== Load Initial Settings |
To begin, open the AD9129 SPI application (Start > Programs > Analog Devices > AD9129 > AD9129_27 SPI). The screen should look similar to Figure 3 on the Common tab. The AD9129 SPI loads default settings that should be usable for most applications. | To begin, open the AD9129 SPI application (Start > Programs > Analog Devices > AD9129 > AD9129_27 SPI). The screen should look similar to Figure 3 on the Common tab. The AD9129 SPI loads default settings that should be usable for most applications. | ||
+ | |||
{{ : | {{ : | ||
<WRAP clear> | <WRAP clear> | ||
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<WRAP centeralign> | <WRAP centeralign> | ||
- | === Configure Hardware === | + | ==== Configure Hardware |
Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. The spectrum analyzer can be configured with Start Frequency = 20 MHz, Stop Frequency 1 GHz, and Resolution Bandwidth of 100 kHz. Use an Average/RMS detector setting, and choose Input Attenuation to be 10 dB. This can be adjusted later if indications are that the analyzer is causing degradations (warnings on the analyzer itself, or third order products appearing on the output spectrum.). The potentiometer should be tuned so that VAGC, the automatic gain control voltage for the power amplifier, is 1.2 V to replicate the following example measurements. | Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. The spectrum analyzer can be configured with Start Frequency = 20 MHz, Stop Frequency 1 GHz, and Resolution Bandwidth of 100 kHz. Use an Average/RMS detector setting, and choose Input Attenuation to be 10 dB. This can be adjusted later if indications are that the analyzer is causing degradations (warnings on the analyzer itself, or third order products appearing on the output spectrum.). The potentiometer should be tuned so that VAGC, the automatic gain control voltage for the power amplifier, is 1.2 V to replicate the following example measurements. | ||
- | === Program the PLL === | + | ==== Program the PLL ==== |
Open the ADF4350 SPI application (Start> | Open the ADF4350 SPI application (Start> | ||
+ | |||
{{ : | {{ : | ||
<WRAP clear> | <WRAP clear> | ||
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The PLL and the chosen reference crystal do not allow for as much frequency precision as the DPG, which specifies its sample frequency down to tens of Hertz. A suggested accuracy for this evaluation board is 100 kHz. To achieve this level of precision, the “Reference Divider” is changed to 250 so that the “PFD Frequency” changes to 0.100 MHz. Then, in the “RF Frequency” section, the “Output Frequency” box should be changed to 2305 MHz to most closely match the DPG sample frequency of 2.30503091 GHz. The discrepancy between the data sample frequency and the programmed clock frequency may create some low level distortion, but the effects have proven negligible in lab. The rest of the settings may be left in their default states. Click the “Write All Reg” button, and the boxes along the bottom of the screen should change from green to grey, indicating that the registers have been programmed. | The PLL and the chosen reference crystal do not allow for as much frequency precision as the DPG, which specifies its sample frequency down to tens of Hertz. A suggested accuracy for this evaluation board is 100 kHz. To achieve this level of precision, the “Reference Divider” is changed to 250 so that the “PFD Frequency” changes to 0.100 MHz. Then, in the “RF Frequency” section, the “Output Frequency” box should be changed to 2305 MHz to most closely match the DPG sample frequency of 2.30503091 GHz. The discrepancy between the data sample frequency and the programmed clock frequency may create some low level distortion, but the effects have proven negligible in lab. The rest of the settings may be left in their default states. Click the “Write All Reg” button, and the boxes along the bottom of the screen should change from green to grey, indicating that the registers have been programmed. | ||
- | === Enable the PLL === | + | ==== Enable the PLL ==== |
- | On the “PLL” tab, the “Controller Ena” button should be green. Click the " | + | On the “PLL” tab, the “Controller Ena” button should be green. Click the " |
{{ : | {{ : | ||
<WRAP clear> | <WRAP clear> | ||
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<WRAP centeralign> | <WRAP centeralign> | ||
+ | ==== Load Pattern from the DPG2 ==== | ||
+ | Open DPGDownloader (Start > Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9129, as indicated in the “Evaluation Board” drop-down list, and select it. For this evaluation board, LVDS is the only valid Port Configuration, | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | Click on “Add Generated Waveform”, | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | Next, in the lower portion of the screen, select “1I: CIFR Vector (I)” as the Data Vector. The other options can be left at their default values. The Data Clock Out (DCO) frequency from the AD9129 should be reported in the Data Clock Frequency window as roughly 576.25 MHz. | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | Make sure the DPG2 unit is powered up and the AD9129 eval board is plugged into it correctly. Click the " | ||
+ | ==== Enable the LVDS Controller ==== | ||
+ | On the AD9129 SPI GUI’s “DLL” tab, the “DUTY Corr Ena” button and the “DLL_ENA” button should be green (selected). Click the ({{: | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | In rare cases, the data link may have gotten corrupted and the registers not programmed correctly. In these cases, the output of the DAC will show significantly degraded performance. To remedy this situation, click the “DUTY Corr Ena” button and the “DLL_ENA” buttons, and then click the ({{: | ||
+ | |||
+ | ==== Result ==== | ||
+ | The final result should be a single 256-QAM carrier centered at 70 MHz, as shown in Figure 10. An attenuation of 30 dB was used in this measurement, | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | ==== Full Band Measurement ==== | ||
+ | To check for flatness across the full cable band, the user can create a new vector or load the vector included in the EVB document package. To do this, select “Add Data File” in the DPG Downloader window, as shown in Figure 12. | ||
+ | |||
+ | {{ : | ||
+ | <WRAP centeralign> | ||
+ | Then, choose the file called “158Channel2.3GSample0dBbackoff.txt” in the C:\Program Files (x86)\Analog Devices\HSDAC\AD9129 folder. Click the {{: | ||
+ | | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | ===== SPI Software ===== | ||
+ | The AD9129 SPI software is conveniently organized in a series of tabs that groups registers according to their functions. In this way, all registers associated with the fDAC PLL, for example, are on the “PLL” tab, all registers associated with the data clock Delay Locked Loop (DLL) are on the “DLL” tab, and so on. A full description of each register and its settings is given in the AD9129 data sheet. Some of the registers and their functions are described here as they pertain to the AD9129 evaluation board. Please note that some of the screen images in this document may not match exactly with the latest revision of the software, due to ongoing improvements and enhancements to the software. | ||
+ | The full screen layout is shown in Figure 14. The tabs can be seen across the top of the work area, and a “READBACK” area is below the active tab area. This READBACK section is present on each of the tabs, so that the user can quickly assess status of the PLL and DLL lock, as well as parity and the FIFO phase. Each of the tabs is discussed in its own section below. | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | ==== Common Tab ==== | ||
+ | The common tab has selections that apply to the general configuration of the DAC. The Reset bit is set or reset here, as well as basic configuration of the serial port: Short vs. Long mode; SDIO pin as an output or bi-directional, | ||
+ | ==== PLL Tab ==== | ||
+ | |||
+ | <WRAP column 45%> | ||
+ | The PLL tab has functions associated with the DAC clock PLL on it. In addition to the enable bit discussed in the Getting Started section, this tab also has settings associated with the PLL retimer registers, reg 0x33 – 0x38. The interrupt control and status bits associated with the PLL (in regs 0x03 – 0x06) are also in this section. | ||
+ | </ | ||
+ | |||
+ | <WRAP column 50%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear></ | ||
+ | <WRAP right 50% centeralign> | ||
+ | <WRAP clear></ | ||
+ | ==== DLL Tab ==== | ||
+ | <WRAP column 45%> | ||
+ | The DLL tab has the DLL Enable and Duty Cycle Correction Enable bits as discussed in the Getting Started section. Additional status bits associated with the Data interface DLL are also on this tab, including lock status bits, lock lost bit, warning bits, etc. These are mostly located in the Data Control and Data Status registers, regs 0x0A – 0x0F. The bypass delay cell area is for test only and can be ignored. | ||
+ | </ | ||
+ | <WRAP column 50%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear></ | ||
+ | <WRAP right 50% centeralign> | ||
+ | <WRAP clear></ | ||
+ | ==== FIFO Tab ==== | ||
+ | <WRAP column 45%> | ||
+ | The FIFO tab has controls and status lights associated with the data interface FIFO. For most uses of the AD9129 EVB, these controls can be left in their default state, and there is no need to change them in the SPI. For more details on the FIFO’s operation and the control and status registers for it, please consult the AD9129 Data Sheet. The FIFO registers are located in address range 0x11 – 0x17. | ||
+ | </ | ||
+ | <WRAP column 50%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear></ | ||
+ | <WRAP right 50% centeralign> | ||
+ | <WRAP clear></ | ||
+ | ==== Parity Tab ==== | ||
+ | <WRAP column 45%> | ||
+ | Similar to the FIFO tab, the Parity tab can be left in its default state for most uses of the AD9129 EVB. Parity can be enabled and disabled on this tab, and Even or Odd Parity can be chosen. The parity counter values are also shown. These controls and status bits are associated with the parity registers located at addresses 0x5C – 0x5E. The parity interrupts are in the Interrupt Control and Status registers, 0x03 – 0x06. | ||
+ | To reset the parity counters, click the PARITY_FALL_RESET and PARITY_RISE_RESET buttons, then press the {{: | ||
+ | </ | ||
+ | <WRAP column 50%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear></ | ||
+ | <WRAP right 50% centeralign> | ||
+ | <WRAP clear></ | ||
+ | ==== Power Control (PD) Tab ==== | ||
+ | <WRAP column 45%> | ||
+ | The Power Control, or Power Down, tab contains individual controls to power down various blocks on the AD9129. These are associated with the power down registers, 0x01 and 0x02. | ||
+ | </ | ||
+ | <WRAP column 50%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear></ | ||
+ | <WRAP right 50% centeralign> | ||
+ | <WRAP clear></ | ||
+ | ==== Analog Tab ==== | ||
+ | <WRAP column 45%> | ||
+ | On the Analog tab, the Full Scale Current of the DAC output can be set by using the increment/ | ||
+ | </ | ||
+ | <WRAP column 50%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear></ | ||
+ | <WRAP right 50% centeralign> | ||
+ | <WRAP clear></ | ||
+ | ==== Save/Load Tab ==== | ||
+ | <WRAP column 45%> | ||
+ | The Save/Load tab enables a different way of configuring the AD9129. The “Save” function allows a user to save to a file all of the settings currently set in the various tabs. The “Load” function allows these settings to be recalled and loaded at a later date. While useful in some situations, this method of loading saved settings does not modify the screens or the tabs, it simply loads the settings directly to the DAC, so it can be confusing to use this function. It is recommended that the user begin with the user GUI and tab interface, and only use this “Save/ | ||
+ | </ | ||
+ | <WRAP column 50%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear></ | ||
+ | <WRAP right 50% centeralign> | ||
+ | <WRAP clear></ | ||