The EVAL-ADG1412LEBZ is the evaluation board for the ADG1412L. The ADG1412L contains four independent single-pole, single-throw (SPDT) switches that can be turned on with Logic 1. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked.
An external VL supply pin provides logic control flexibility for lower logic controls. The ADG1412L is both 1.2 V and 1.8 V JEDEC Standard compliant.
Figure 1 shows the EVAL-ADG1412LEBZ in a typical evaluation setup. The EVAL-ADG1412LEBZ is placed in the center of the evaluation board, and four test points and SMB sockets are provided to connect to each of the sources and drain inputs. Three screw terminals are used to power the device. A 5-pin header is provided for user-defined digital voltage if required.
Full specifications on the ADG1412L are available in the ADG1412L data sheet available from Analog Devices, Inc., and should be consulted in conjunction with this user guide when using the evaluation board.
Connector P1 provides access to the supply pins of the ADG1412L. VDD, GND, and VSS on P1 link to the appropriate pins on the ADG1412L. For dual-supply voltages, the evaluation board can be powered at ±5 V or ±15 V. For single-supply voltages, the GND and VSS terminals must be connected and power the evaluation board with 12 V. Additionally, 1.1 V to 1.95 V is supplied to the VL pin of the ADG1412L.
Two-screw connectors, P3, P4, P5, and P6 are provided to connect to both the source and drain pins of the ADG1412L. Additional subminiature Version B (SMB) connector pads are available if extra connections are required.
Each trace on the source and drain side includes two sets of 0603 pads, which can place a load on the signal path to the ground. A 0 Ω resistor is placed in the signal path and can be replaced with a user-defined value. The resistor combined with the 0603 pads can create a simple resistor-capacitor (RC) filter.
A number of link options are provided on the EVAL-ADG1412LEBZ board that must be set for the required operating conditions before use. Table 1 shows the summary of the link headers and how they are used on the evaluation board. The functions of these link options are described in detail in Table 2.
Table 1. Link Options
|JP9 to JP12
Table 2. Link Functions
|JP9 to JP12
|This link selects the source of the IN voltage supplied to the ADG1412L.
|Position A selects VL from P2.
|Position B selects the 0 V or GND.
The parallel interface of the ADG1412L is controlled manually using the link headers of JP9 to JP12, or it can be accessed using the SMB connectors, IN1 to IN4. To use the SMB connectors, remove the link headers of JP9 to JP12.
Figure 2. EVAL-ADG1412LEBZ Schematic 1
Figure 3. EVAL-ADG1412LEBZ Silkscreen
Figure 4. EVAL-ADG1412LEBZ Top Layer
Figure 5. EVAL-ADG1412LEBZ Layer 2
Figure 6. EVAL-ADG1412LEBZ Layer 3
Figure 7. EVAL-ADG1412LEBZ Bottom Layer
|C1 to C3, C7 to C9
|50 V, X7R Multilayer Ceramic Capacitor, 0.1 µF, 0603
|C4 to C6
|50 V, Tantalum Capacitor, 10 µF, Size D
|C10 to C17
|R1 to R8
|R9 to R16
|Resistor, 0 Ω, 0603, 1%
|J1 to J13
|50 Ω, SMB socket, do not insert
|T1 to T15
|Red test point
|TP16 to TP20
|Black test point
|Header RA 3.81mm with plug
|Through hole header, 5P
|P3 to P6
|2-Position Terminal Block, 5 mm
|JP9 to JP12
|3-pin SIL header and shorting link
|1.5 Ω On-resistance, Quad SPDT Switch with 1.2 V and 1.8 V JEDEC Logic Compliance
|ANALOG DEVICES, INC.