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resources:eval:ad9695-1300ebz [19 Jul 2018 16:15] – [Configuring the Board] Judy Chuiresources:eval:ad9695-1300ebz [29 Aug 2019 20:20] – [Configuring the Board] Judy Chui
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   - The [[ads7-v2|ADS7-V2EBZ]] should appear in the Device Manager as shown in Figure 6.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:0.png?direct&300 |}}</WRAP><WRAP centeralign>//Figure 6. Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP>   - The [[ads7-v2|ADS7-V2EBZ]] should appear in the Device Manager as shown in Figure 6.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:0.png?direct&300 |}}</WRAP><WRAP centeralign>//Figure 6. Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP>
   - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed as shown in Figure 6, unplug all USB devices from the PC, uninstall and re-install ACE and restart the hardware setup from step 1.   - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed as shown in Figure 6, unplug all USB devices from the PC, uninstall and re-install ACE and restart the hardware setup from step 1.
-  - On the AD9695 evaluation board, provide a clean, low jitter 625 MHz clock source to connector **P202** (preferably via a shielded RG-58 50 Ω coaxial cable) and set the amplitude to 10 dBm. This is the ADC Sample Clock.+  - On the AD9695 evaluation board, provide a clean, low jitter 1300 MHz clock source to connector **P202** (preferably via a shielded RG-58 50 Ω coaxial cable) and set the amplitude to 10 dBm. This is the ADC Sample Clock.
   - On the ADS7-V2, provide a clean, low jitter clock source to connector **J3** and set the amplitude to 10 dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio </m> </WRAP> <WRAP centeralign><m> Nprime=8 or 16 </m></WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP> <WRAP centeralign> <sub>//(Default Nprime = 16; DCM = Chip Decimation Ratio (DCM = 1 for Full Bandwidth Mode); M = Virtual Converters; L = Lanes)//</sub> </WRAP>   - On the ADS7-V2, provide a clean, low jitter clock source to connector **J3** and set the amplitude to 10 dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio </m> </WRAP> <WRAP centeralign><m> Nprime=8 or 16 </m></WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP> <WRAP centeralign> <sub>//(Default Nprime = 16; DCM = Chip Decimation Ratio (DCM = 1 for Full Bandwidth Mode); M = Virtual Converters; L = Lanes)//</sub> </WRAP>
   - On the AD9695 evaluation board, connect a clean signal generator with low phase noise to **J101** or **J104** via coaxial cable for channels A and B respectively. It is recommended to use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency.   - On the AD9695 evaluation board, connect a clean signal generator with low phase noise to **J101** or **J104** via coaxial cable for channels A and B respectively. It is recommended to use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency.
resources/eval/ad9695-1300ebz.txt · Last modified: 14 Jan 2021 05:11 by Robin Getz

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