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resources:eval:ad9694-500ebz [19 Feb 2019 21:01] – [Configuring the Board] Judy Chui | resources:eval:ad9694-500ebz [20 May 2022 17:52] (current) – [Visual Analog Setup] Judy Chui | ||
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===== Software Needed ===== | ===== Software Needed ===== | ||
* VisualAnalog [[ftp:// | * VisualAnalog [[ftp:// | ||
- | * ACE [[https:// | + | * ACE [[/ |
===== Design and Integration Files ===== | ===== Design and Integration Files ===== | ||
- | *[[https:// | + | * {{ :eval:9694_board_files_ce04.zip |AD9694CE04A schematic, BOM, layout files}} |
===== Equipment Needed ===== | ===== Equipment Needed ===== | ||
* Analog signal source and antialiasing filter | * Analog signal source and antialiasing filter | ||
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- The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ : | - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ : | ||
- If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | ||
- | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector | + | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector |
- On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:< | - On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:< | ||
- On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
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- On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9694 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode. If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ : | - On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9694 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode. If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ : | ||
- Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ : | - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ : | ||
- | - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to 2x the input clock. For example, if the input clock to the AD9694 is 368.64 MHz then set the **Clock Frequency (MHz)** to 737.28 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel).{{ : | + | - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to match the sample |
- If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ : | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ : | ||
- | - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked. | + | - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked. |
- Click **OK** | - Click **OK** | ||
==== ACE Setup ==== | ==== ACE Setup ==== | ||
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- When making changes to the DDC settings the **DDC Soft Reset** must be written afterwards. | - When making changes to the DDC settings the **DDC Soft Reset** must be written afterwards. | ||
==== Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode ==== | ==== Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode ==== | ||
- | - The first item to configure in Visual Analog is the input clock frequency. | + | - The first item to configure in Visual Analog is the input clock frequency. |
- | - In this example, with an input clock of 368.64MHz, the output sample rate is 184.32MSPS. | + | - In this example, with a sample |
- Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | ||
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Adjust the input signal to -1.4 dBFS or less in the FFT in Visual Analog (this accounts for the approximately -0.4 dB loss in the DDC. Recall that the mixing process incurs a 6dB additional loss; the signal amplitude is -7.4 dBFS in this plot. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Adjust the input signal to -1.4 dBFS or less in the FFT in Visual Analog (this accounts for the approximately -0.4 dB loss in the DDC. Recall that the mixing process incurs a 6dB additional loss; the signal amplitude is -7.4 dBFS in this plot. |