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resources:eval:ad9694-500ebz [14 Jan 2021 05:11] – user interwiki links Robin Getzresources:eval:ad9694-500ebz [20 May 2022 17:52] (current) – [Visual Analog Setup] Judy Chui
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   - On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9694 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode.  If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ :resources:eval:newcanvas9694.jpg?nolink |}}<WRAP centeralign>//Selecting the [[adi>AD9694|AD9694]] canvas //</WRAP>   - On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9694 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode.  If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ :resources:eval:newcanvas9694.jpg?nolink |}}<WRAP centeralign>//Selecting the [[adi>AD9694|AD9694]] canvas //</WRAP>
   - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ :resources:eval:9694_program_FPGA.png?nolink |}}<WRAP centeralign>//Programming the [[ads7-v2|ADS7-V2EBZ]]//</WRAP>   - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ :resources:eval:9694_program_FPGA.png?nolink |}}<WRAP centeralign>//Programming the [[ads7-v2|ADS7-V2EBZ]]//</WRAP>
-  - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to 2x the input clock. For example, if the input clock to the AD9694 is 368.64 MHz then set the **Clock Frequency (MHz)** to 737.28 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel).{{ :resources:eval:9694_data_capture_settings_general.png |}}<WRAP centeralign>//Changing the ADC Capture Settings//</WRAP>+  - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to match the sample clock. For example, if the sample clock of the AD9694 is 368.64 MHz then set the **Clock Frequency (MHz)** to 368.64 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel).{{ :resources:eval:9694_data_capture_settings_general.png |}}<WRAP centeralign>//Changing the ADC Capture Settings//</WRAP>
   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Expanding Display in VA//</WRAP>   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Expanding Display in VA//</WRAP>
   - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked.   - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked.
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     - When making changes to the DDC settings the **DDC Soft Reset** must be written afterwards.  To do so, select **DDC Held in Reset** from the drop down menu in the block diagram.  Then click **Apply Changes** in the upper left of the AD9694 Device view in ACE.  Next, select **Normal Operation** from the drop down menu in the block diagram and then click **Apply Changes** once again.  This process resets the DDC and then places the DDC back into normal operating mode.  This must be done for each pair (Pair AB and/or Pair CD) for which DDC changes have been applied. {{ :resources:eval:9694_ace_device_view_1ddc_complexinout_ddc_softreset.png?nolink |}}<WRAP centeralign>//Pair AB: Channel A and Channel B DDC0 Settings with DDC Soft Reset//</WRAP>     - When making changes to the DDC settings the **DDC Soft Reset** must be written afterwards.  To do so, select **DDC Held in Reset** from the drop down menu in the block diagram.  Then click **Apply Changes** in the upper left of the AD9694 Device view in ACE.  Next, select **Normal Operation** from the drop down menu in the block diagram and then click **Apply Changes** once again.  This process resets the DDC and then places the DDC back into normal operating mode.  This must be done for each pair (Pair AB and/or Pair CD) for which DDC changes have been applied. {{ :resources:eval:9694_ace_device_view_1ddc_complexinout_ddc_softreset.png?nolink |}}<WRAP centeralign>//Pair AB: Channel A and Channel B DDC0 Settings with DDC Soft Reset//</WRAP>
 ==== Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode ==== ==== Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode ====
-  - The first item to configure in Visual Analog is the input clock frequency.  This needs to be set to twice the frequency of the input clock.  Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.  Also, make sure that the output data is set to *Ch. DDC0 Data*.{{ :resources:eval:6684_data_capture_settings_ddc0.png?nolink |}}<WRAP centeralign>//AD9694 FFT Data Capture Settings//</WRAP> +  - The first item to configure in Visual Analog is the input clock frequency.  This needs to be set to twice the frequency of the input clock.  Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the sample clock frequency so 368.64 is entered into VisualAnalog.  Also, make sure that the output data is set to *Ch. DDC0 Data*.{{ :resources:eval:6684_data_capture_settings_ddc0.png?nolink |}}<WRAP centeralign>//AD9694 FFT Data Capture Settings//</WRAP> 
-  - In this example, with an input clock of 368.64MHz, the output sample rate is 184.32MSPS.  The  JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.4.4 (L.M.F).  The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "Configuring the Board"). +  - In this example, with a sample clock of 368.64MHz, the output sample rate is 184.32MSPS.  The  JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.4.4 (L.M.F).  The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "Configuring the Board"). 
   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:9694_2ddc_complex_inout_ncopassthrough_fft_fin345p1mhz.png?800 |}}<WRAP centeralign>//AD9694 FFT with DDC0 Enabled//</WRAP>   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:9694_2ddc_complex_inout_ncopassthrough_fft_fin345p1mhz.png?800 |}}<WRAP centeralign>//AD9694 FFT with DDC0 Enabled//</WRAP>
   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Adjust the input signal to -1.4 dBFS or less in the FFT in Visual Analog (this accounts for the approximately -0.4 dB loss in the DDC. Recall that the mixing process incurs a 6dB additional loss; the signal amplitude is -7.4 dBFS in this plot.   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Adjust the input signal to -1.4 dBFS or less in the FFT in Visual Analog (this accounts for the approximately -0.4 dB loss in the DDC. Recall that the mixing process incurs a 6dB additional loss; the signal amplitude is -7.4 dBFS in this plot.
resources/eval/ad9694-500ebz.txt · Last modified: 20 May 2022 17:52 by Judy Chui

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