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resources:eval:ad9694-500ebz [19 Feb 2019 21:03] – [Visual Analog Setup] Judy Chuiresources:eval:ad9694-500ebz [13 Jun 2019 16:39] – "J204" was a typo, so I correct it to "J203". ShahEd Shahir
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   - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ :resources:eval:9694_ads7v2_devmgr.png?nolink&300 |}}<WRAP centeralign>//Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP>   - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ :resources:eval:9694_ads7v2_devmgr.png?nolink&300 |}}<WRAP centeralign>//Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP>
   - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1.   - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1.
-  - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J204 and set the amplitude to 14dBm. This is the ADC Sample Clock.+  - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J203 and set the amplitude to 14dBm. This is the ADC Sample Clock.
   - On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP>   - On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP>
   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) If providing an input clock with a divide-by-1 setting in the AD9694 make sure the clock source has a 50% duty cycle.  For optimum SNR performance use the clock divider with a divide ratio of 2 or higher to minimize the impact of the phase noise from the input clock source.   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) If providing an input clock with a divide-by-1 setting in the AD9694 make sure the clock source has a 50% duty cycle.  For optimum SNR performance use the clock divider with a divide ratio of 2 or higher to minimize the impact of the phase noise from the input clock source.
resources/eval/ad9694-500ebz.txt · Last modified: 20 May 2022 17:52 by Judy Chui

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