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resources:eval:ad9684-500ebz [17 Nov 2022 03:15] – [Configuring the Board] John Xavier Toledoresources:eval:ad9684-500ebz [17 Nov 2022 03:15] – [Visual Analog Setup] John Xavier Toledo
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   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 6){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Figure 6. Expanding Display in VA//</WRAP>   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 6){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Figure 6. Expanding Display in VA//</WRAP>
   - Click the **Settings** button in the **ADC Data Capture** block to view the capture size as shown in Figure 7 {{ :eval:ad9684_capture_settings.png?400 |}}<WRAP centeralign>//Figure 7. Setting the capture length//</WRAP>   - Click the **Settings** button in the **ADC Data Capture** block to view the capture size as shown in Figure 7 {{ :eval:ad9684_capture_settings.png?400 |}}<WRAP centeralign>//Figure 7. Setting the capture length//</WRAP>
-  - On the **General** tab make sure the clock frequency is set to **500MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) per channel. The HSC-EVALE FPGA software supports up to 256K FFT capture (128K per channel){{ :eval:ad9684_500m_capture_settings.png?400 |}}<WRAP centeralign>//Figure 8. Setting the clock frequency //</WRAP> +  - On the **General** tab make sure the clock frequency is set to **500MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) per channel. The [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] FPGA software supports up to 256K FFT capture (128K per channel){{ :eval:ad9684_500m_capture_settings.png?400 |}}<WRAP centeralign>//Figure 8. Setting the clock frequency //</WRAP> 
-  - Click on the **Capture Board** tab and browse to the **ad9684_evalez_05202014_0903am.mcs** file. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the HSC-EVALE board indicating that the FPGA has been correctly programmed. The bin file is available at the **Design and Integration Files** section+  - Click on the **Capture Board** tab and browse to the **ad9684_evalez_05202014_0903am.mcs** file. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] board indicating that the FPGA has been correctly programmed. The bin file is available at the **Design and Integration Files** section
   - Click **OK**   - Click **OK**
 ==== SPIController Setup ==== ==== SPIController Setup ====
resources/eval/ad9684-500ebz.txt · Last modified: 13 Jan 2023 02:42 by John Xavier Toledo

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