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— | resources:eval:ad9680-1000ebz [23 Oct 2023 08:25] – [Troubleshooting Tips] Janadrian Alipio | ||
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+ | ====== EVALUATING THE AD9680/ | ||
+ | ===== Preface ===== | ||
+ | This user guide describes the [[adi> | ||
+ | ^ Evaluation Board Part Number | ||
+ | | <fc # | ||
+ | | <fc # | ||
+ | | <fc # | ||
+ | | <fc # | ||
+ | | <fc # | ||
+ | | <fc # | ||
+ | | <fc # | ||
+ | | <fc # | ||
+ | | <fc # | ||
+ | | AD9234-LF1000EBZ | ||
+ | | AD9234-LF500EBZ | ||
+ | \\ | ||
+ | The [[adi> | ||
+ | |||
+ | ===== AD9680/ | ||
+ | {{ : | ||
+ | <WRAP centeralign>// | ||
+ | {{ : | ||
+ | <WRAP centeralign>// | ||
+ | Figure 3 below compares the bandwidth available on the AD9680/ | ||
+ | {{ : | ||
+ | <WRAP centeralign>// | ||
+ | |||
+ | ===== Typical Measurement Setup ===== | ||
+ | The [[adi> | ||
+ | {{ : | ||
+ | <WRAP centeralign>// | ||
+ | <note important> | ||
+ | {{ : | ||
+ | <WRAP centeralign>// | ||
+ | |||
+ | ===== Features ===== | ||
+ | * Full featured evaluation board for the [[adi> | ||
+ | * AD9680-1250EBZ | ||
+ | * AD9680-1000EBZ, | ||
+ | * AD9680-820EBZ, | ||
+ | * AD9680-500EBZ, | ||
+ | * AD9234-1000EBZ, | ||
+ | * AD9234-500EBZ, | ||
+ | * SPI interface for setup and control | ||
+ | * Wide band Balun driven input for the AD9680-1250EBZ, | ||
+ | * Double balun input for AD9680-LF1000EBZ, | ||
+ | * No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC. | ||
+ | * VisualAnalog® and SPI controller software interfaces. | ||
+ | * ACE (Analysis | Control | Evaluation) software interface. | ||
+ | * On-board Crystal oscillator for AD9680-LF1000EBZ, | ||
+ | |||
+ | ===== Helpful Documents ===== | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | ===== Software Needed ===== | ||
+ | * [[adi> | ||
+ | |||
+ | ===== Design and Integration Files ===== | ||
+ | * {{: | ||
+ | * {{: | ||
+ | |||
+ | ===== Equipment Needed ===== | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[adi> | ||
+ | * PC running Windows® | ||
+ | * USB 2.0 High-speed A to B Cable | ||
+ | * Low phase noise analog input source and antialiasing filter | ||
+ | * Low phase noise sample clock source | ||
+ | * Reference clock source | ||
+ | |||
+ | ===== Getting Started ===== | ||
+ | This section provides quick start procedures for using the evaluation board for AD9680 or AD9234. | ||
+ | |||
+ | ===== Configuring the Board ===== | ||
+ | Before using the software for testing, configure the evaluation board as follows: | ||
+ | - Connect the evaluation board to the [[adi> | ||
+ | - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P7 on the [[adi> | ||
+ | - Connect the Standard-B USB port of the [[adi> | ||
+ | - Turn on the [[adi> | ||
+ | - The [[adi> | ||
+ | - If the Device Manager does not show the [[adi> | ||
+ | - On the ADC evaluation board, provide a clean, low jitter 1.25 GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock. | ||
+ | - On the ADC evaluation board, provide a clean, low jitter clock source to connector J804 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:< | ||
+ | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
+ | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
+ | |||
+ | ===== Software Setup ===== | ||
+ | <WRAP indent> | ||
+ | < | ||
+ | <hidden ACE Setup> | ||
+ | - Download and install [[adi> | ||
+ | - The AD9680 ACE plug-in can be found under the [[adi> | ||
+ | - Once the .acezip file has been downloaded from the Analog Devices website, right click on it and install the plug-in, or double click to install. | ||
+ | - Click Start -> All Programs -> Analog Devices -> ACE -> ACE | ||
+ | - The AD9680 plug-in should appear as in Figure 7 if installed correctly.< | ||
+ | - If the AD9680 plug-in does not appear, or no board is detected, make sure the ADS7-V2 is powered on and the evaluation board is properly connected. Make sure that ACE has been updated to the most recent version and the necessary plug-ins have been installed.< | ||
+ | - Double click on the plug-in to open it. This will open the AD9680 Board View.< | ||
+ | - Double click on the blue AD9680 chip (in the middle of the board) to open up the Chip View.< | ||
+ | </ | ||
+ | |||
+ | <hidden Visual Analog & SPI Controller Setup> | ||
+ | **Visual Analog Setup** | ||
+ | - Click Start < | ||
+ | - On the VisualAnalog “New Canvas” window, click **ADC**< | ||
+ | - At this point, VisualAnalog will automatically detect the evaluation board and the FPGA data capture board and ask if it can program the FPGA with the appropriate bin file. This is shown in figure 11. Programming the FPGA will provide power to the evaluation board.{{ : | ||
+ | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 12){{ : | ||
+ | - Click the **Settings** button in the **ADC Data Capture** block as shown in Figure 13{{ : | ||
+ | - On the **General** tab make sure the clock frequency is set to the appropriate sample rate (eg. **1250 MHz or 1000 MHz**). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel){{ : | ||
+ | - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked.{{ : | ||
+ | - Click **OK** | ||
+ | **SPI Controller Setup** | ||
+ | - Click Start < | ||
+ | - Select the appropriate configuration file when prompted. | ||
+ | - In the **Global** tab, under the **Generic Read/ | ||
+ | - Individual Channel control for **ADC A** and **ADC B** are done using the **Device Index Register (0x008)** in the Global tab.{{ : | ||
+ | - Under **ADC A** and **ADC B** tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with: | ||
+ | - **Chip Configuration Register (0x002)**: This option allows the channel to be powered on. | ||
+ | - **Buffer Current Setting (0x018)**: This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, | ||
+ | - **Analog Input Differential Termination (0x016)**: This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, | ||
+ | - **Input Full Scale Range (0x025)**: At high input frequencies, | ||
+ | </ | ||
+ | </ | ||
+ | |||
+ | ===== Sample Configuration 1: Full Bandwidth Mode ===== | ||
+ | <WRAP indent> | ||
+ | <hidden ACE Configuration> | ||
+ | - Under **Initial Configuration** at board view, set the clock input to 1250 MHz. Change the **Clock Divide Ratio** to divide by 1. Change the **Chip Operation Mode** to full bandwidth mode. Change the number of **Lane** to 4. Change the number of **Virtual Converter** to 2. Change the number of **Octets per Frame** to 1. Click **Apply** to apply the chip settings. Set the reference clock to 625 MHz to match these settings.{{ : | ||
+ | - The chip view will update to reflect the changes made to the board. If any changes are made, the chip can be read by clicking the **Read All button**.{{ : | ||
+ | - Set the **PLL Control** serial lane rate to 6.25 Gbps to 12.5 Gbps and click **Apply Changes**. The decision to use Maximum Lane Rate (6.25 Gbps to 12.5 Gbps) or Low Lane Rate (3.125 Gbps to 6.25 Gbps) should be based on the **Lane Line Rate** that was calculated in [[/ | ||
+ | - Issue a **Data Path Reset** to the AD9680 by clicking its checkbox and clicking **Apply Changes**. The data path reset bit will automatically self clear.{{ : | ||
+ | - If the **PLL Locked** indicator lights up, you can reset it by powering down the JESD link using the **Link Control** dropdown box, and clicking **Apply Changes**.{{ : | ||
+ | - Enable the **Link Control** again and **Apply Changes**.{{ : | ||
+ | - Click **Apply** at **AD9680 Configuration** and then **Proceed to Analysis**. This is ACE's Analysis tool for the data from the ADC, displaying both sample plots (Waveform) and FFTs. Click on **FFT** and **Run Once** to capture once.{{ : | ||
+ | - **Channel A** and **Channel B** can be selected individually to display their **FFTs**.{{ : | ||
+ | - A successful capture is shown below, with a filtered 170 MHz signal inputted at on Channel A.{{ : | ||
+ | - To save the FFT plot, click on **Export** button at **Analysis Results** tab and save it to a location of choice. | ||
+ | </ | ||
+ | |||
+ | <hidden Visual Analog & SPI Controller Configuration> | ||
+ | **SPI Controller Configuration** | ||
+ | - Set the ADC Configuration Registers in **ADCBase0** tab. Write **Chip Mode Control Register** address 0x200 to **Full Bandwidth Mode** and **Chip Decimation Ratio Control Register** 0x201 to **Full Sample Rate**.{{ : | ||
+ | - For JESD204B setting, proceed to **ADCBase3** tab. Check the **Serial Transmit Power Down** box in **JESD204B Link Control Register (0x571)**.{{ : | ||
+ | - Set the Lane Rate setting register 0x56E to **Maximum Lane Rate**. The decision to use **Maximum Lane Rate** mode or **Low Lane Rate** mode should be based on the Lane Line Rate that was calculated in [[/ | ||
+ | - Set the **JESD204B Quick Configuration register (0x570)**. For 1000MSPS operation with **NO** DDCs (//Full Bandwidth Mode//), the values for **L.M.F** are **4.2.1**{{ : | ||
+ | - Proceed to **ADCBase4** tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.{{ : | ||
+ | - On address **0x58F** (see figure 33), change the Converter Resolution to **14** for AD9680 (12 for AD9234). | ||
+ | - Back to **ADCBase3** tab, uncheck the **Serial Transmit Power Down** box in JESD204B Link Control Register (0x571), see figure 30. | ||
+ | - After the quick configuration setting is completed, the **PLL Lock Detect register 0x56F** will read **0x80** to denote a lock. The SPIController interface will show a " | ||
+ | **Obtaining an FFT on Visual Analog** | ||
+ | - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 35.{{ : | ||
+ | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window. | ||
+ | - To save the FFT plot do the following: | ||
+ | - Click on the **Float Form button** in the FFT window.{{ : | ||
+ | - Click on **File < | ||
+ | </ | ||
+ | </ | ||
+ | |||
+ | ===== Sample Configuration 2: Two ADCs Plus Two DDCs, Decimate by 4 ===== | ||
+ | <WRAP indent> | ||
+ | <hidden ACE Configuration> | ||
+ | - Under **Initial Configuration** at board view, set the clock input to 1250 MHz. Change the **Clock Divide Ratio** to divide by 1. Change the **Chip Operating Mode** for two DDCs. The DDC settings will become available, set the **Decimation Ratio** select " | ||
+ | - The **Chip View** will update to reflect the changes. Click on the **NCO block** to change the Numerically Controlled Oscillator' | ||
+ | - Enable the 6dB gain for the DDC at the amplifier block drop down menu.{{ : | ||
+ | - Set the **Mixer** to Real. Click **Apply Changes** to apply configuration at **DDC0**.{{ : | ||
+ | - Navigate to the second DDC (**DDC1**) and make the same changes.{{ : | ||
+ | - Set the **DDC Soft Reset** to **DDC Held in Reset** in dropdown menu to soft reset the DDC, and click **Apply Changes**.{{ : | ||
+ | - Change the **DDC Soft Reset** to **Normal Operation** in dropdown menu, and click **Apply Changes**. And then click on **Proceed to Analysis**.{{ : | ||
+ | - In **Analysis** tool, run a capture once. DDC0 can be selected from Channel A and DDC1 can be selected from Channel B (see figure 45). | ||
+ | - A successful capture is shown below, with a filtered 170 MHz signal inputted on **Channel A / DDC0**.{{ : | ||
+ | </ | ||
+ | |||
+ | <hidden Visual Analog & SPI Controller Configuration> | ||
+ | **Visual Analog & SPI Controller Configuration** | ||
+ | - In the [[/ | ||
+ | - In the [[/ | ||
+ | - For **DDC Settings**, proceed to **ADCBase1** tab and configure DDC0 and DDC1 Control Registers with corresponding addresses of **0x310** and **0x330**, respectively, | ||
+ | - For frequency tuning word (FTW), addresses **0x314-315** are set as required by application for DDC0, and addresses **0x334-335** are set as required by application for DDC1. Figure 49 below shows the calculation for NCO Frequency Tuning Word. {{ : | ||
+ | - After setting all DDC registers, go to **Generic Write/ | ||
+ | - For JESD204B setting, proceed to **ADCBase3** tab. Check the **Serial Transmit Power Down** box in **JESD204B Link Control Register (0x571)**.{{ : | ||
+ | - Set the Lane Rate setting register 0x56E to **Maximum Lane Rate**. The decision to use **Maximum Lane Rate** mode or **Low Lane Rate** mode should be based on the Lane Line Rate that was calculated in [[/ | ||
+ | - Set the **JESD204B Quick Configuration register (0x570)**. For 1000 MSPS operation with **2** DDCs (//Two Digital Down Converters// | ||
+ | - Proceed to **ADCBase4** tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on **ADCBase3** tab are reflected.{{ : | ||
+ | - On address **0x58F** (see figure 54), change the Converter Resolution to **14** for AD9680 (12 for AD9234). | ||
+ | - Back to **ADCBase3** tab (se figure 51), uncheck the **Serial Transmit Power Down** box in JESD204B Link Control Register (0x571). | ||
+ | - After the quick configuration setting is completed, the **PLL Lock Detect register 0x56F** will read **0x80** to denote a lock. The SPIController interface will show a " | ||
+ | **Obtaining an FFT on Visual Analog** | ||
+ | - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 56.{{ : | ||
+ | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) | ||
+ | </ | ||
+ | </ | ||
+ | |||
+ | ===== Validating Deterministic Latency Using Subclass 1 Operation ===== | ||
+ | The following .zip files contain the files needed for users to validate subclass 1 operation and observe the latency | ||
+ | *{{: | ||
+ | *{{: | ||
+ | |||
+ | ===== Troubleshooting Tips ===== | ||
+ | ** Evaluation board is not functioning properly ** | ||
+ | * It is possible that a board component has been rendered inoperable by ESD, accidental shorting while probing, etc. Try checking the supply domain voltages of the board while it is powered. They should be as follows: | ||
+ | *< | ||
+ | ^ Domain | ||
+ | | AVDD_1 | ||
+ | | AVDD_1 | ||
+ | | AVDD_2 | ||
+ | | AVDD_1P8 | ||
+ | | DVDD | TP407 | 1.25 V | | ||
+ | | DRVDD | ||
+ | </ | ||
+ | * If a short is detected between any of the supply domains and ground, or an open is detected across fuse chip F400 or F401, a component may have been damaged. | ||
+ | |||
+ | ** Evaluation board is not communicating with the ADS7-V2 / No SPI communication ** | ||
+ | * Make sure that the FPGA on the ADS7-V2 has been programmed - a lit LED DS15 (**FPGA_DONE**) on the top of the ADS7-V2 and a powered fan are good indicators of the FPGA being programmed. | ||
+ | * Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly two-thirds of DRVDD_1. On the ADS7-V2, the common mode voltage should be around 1.2 volts. | ||
+ | * To test SPI operation, attempt to both read and write to register 0x00A (Scratch Pad) using ACE's Register Debugger (Tools -> Register Debugger). This register is an open register available for testing memory reads and writes. If the register reads back the same value written to it, SPI is operational. | ||
+ | * All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication. | ||
+ | * Register 0x000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS7-V2 not being programmed. | ||
+ | |||
+ | ** ACE software fails to capture date ** | ||
+ | * Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips. | ||
+ | * Check the Clock Status register 0x011C to see if the input sample clock is being detected. 0x01 indicates detection, 0x00 indicates no clock detected. Check the signal generator input on connector J801. Try checking the common mode voltage on the clock pins, which should be roughly two-thirds of AVDD_1. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip. | ||
+ | * Check the PLL Locked indicator (see figure 23) or register 0x056F (PLL Status). If the light in the plugin chip view is green or if the register reads back 0x80, the PLL is locked. If it is not locked: | ||
+ | * Check the clock being input to connector J801 (in this guide, 1.25 GHz or 1 GHz depending on the evaluation board). | ||
+ | * Check the JESD204B settings under the Initial Configuration. Reference the [[adi> | ||
+ | * Check the Reference Clock and make sure it matches your JESD settings. | ||
+ | * Make sure P100 (Power Down / Standby Jumper) is not jumped. | ||
+ | |||
+ | ** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ||
+ | * Ensure that the clock to the ADC is supplied. Using SPIController ADCBase0 tab the status of the clock can be read out. See figure 57.{{ : | ||
+ | * Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. This can be done using SPIController (see figure 34 or 55). | ||
+ | |||
+ | ** VisualAnalog indicates that the “FIFO capture timed out” or "FIFO not ready for read back" ** | ||
+ | * Make sure all power and USB connections are secure. | ||
+ | * Make sure that the Reference Clock is ON and set to the appropriate frequency. | ||
+ | | ||
+ | ** FFT plot appears abnormal ** | ||
+ | * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. | ||
+ | * In ACE Analysis tab under CAPTURE -> General -> Encoding (see figure 26), check that the encoding is set to correct number format (two's compliment by default). | ||
+ | * Issue a Data Path Reset through ACE Chip View (see figure 22). | ||
+ | * In VisualAnalog, | ||
+ | * Issue a Data Path Soft Reset through SPIController Global tab (see Figure 23). | ||
+ | |||
+ | ** The FFT plot appears normal, but performance is poor. ** | ||
+ | * Make sure you are using the appropriate band-pass filter on the analog input. | ||
+ | * Make sure the signal generators for the clock and the analog input are clean (low phase noise). | ||
+ | * If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies. | ||
+ | * Make sure the SPIController config file matches the product being evaluated when using the VisualAnalog. | ||
+ | |||
+ | ** The FFT window remains blank after the Run button is clicked ** | ||
+ | * Make sure the evaluation board is securely connected to the [[adi> | ||
+ | * Make sure the FPGA has been programmed by verifying that the Config DONE LED is illuminated on the [[adi> | ||
+ | * Make sure the correct FPGA //bin// file was used to program the FPGA in VisualAnalog. | ||
+ | * Be sure that the correct sample rate is programmed. | ||
+ | * In ACE, check the Board view tab and Chip view tab if the Sampling Frequency is properly set (see figures 8 & 9) | ||
+ | * In VisualAnalog, | ||
+ | * Ensure that the Reference Clock is ON and set to the appropriate frequency. | ||
+ | * Restart ACE software or VisualAnalog/ |