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| — | resources:eval:ad9680-1000ebz [23 Sep 2022 09:43] – [Obtaining an FFT] John Xavier Toledo | ||
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| + | ====== EVALUATING THE AD9680/ | ||
| + | ===== Preface ===== | ||
| + | This user guide describes the [[adi> | ||
| + | ^ Evaluation Board Part Number | ||
| + | | <fc # | ||
| + | | <fc # | ||
| + | | <fc # | ||
| + | | <fc # | ||
| + | | <fc # | ||
| + | | <fc # | ||
| + | | <fc # | ||
| + | | <fc # | ||
| + | | <fc # | ||
| + | | AD9234-LF1000EBZ | ||
| + | | AD9234-LF500EBZ | ||
| + | \\ | ||
| + | The [[adi> | ||
| + | ===== AD9680/ | ||
| + | {{ : | ||
| + | //Figure 1. [[adi> | ||
| + | {{ : | ||
| + | //Figure 2. [[adi> | ||
| + | Figure 3 below compares the bandwidth available on the AD9680/ | ||
| + | //Figure 3. Comparison of Bandwidth on the Normal and the " | ||
| + | |||
| + | ===== Typical Measurement Setup ===== | ||
| + | The [[adi> | ||
| + | {{ : | ||
| + | //Figure 3. Evaluation Board Connection—[[adi> | ||
| + | < | ||
| + | </ | ||
| + | {{ : | ||
| + | //Figure 4. Evaluation Board Connection—[[adi> | ||
| + | </ | ||
| + | ===== Features ===== | ||
| + | * Full featured evaluation board for the [[adi> | ||
| + | * AD9680-1000EBZ, | ||
| + | * AD9680-820EBZ, | ||
| + | * AD9680-500EBZ, | ||
| + | * AD9234-1000EBZ, | ||
| + | * AD9234-500EBZ, | ||
| + | * SPI interface for setup and control | ||
| + | * Wide band Balun driven input for the AD9680-1000EBZ, | ||
| + | * Double balun input for AD9680-LF1000EBZ, | ||
| + | * No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC | ||
| + | * VisualAnalog® and SPI controller software interfaces | ||
| + | * On-board Crystal oscillator for AD9680-LF1000EBZ, | ||
| + | |||
| + | ===== Helpful Documents ===== | ||
| + | * [[adi> | ||
| + | * [[: | ||
| + | * [[adi> | ||
| + | * [[adi> | ||
| + | * [[adi> | ||
| + | * [[adi> | ||
| + | ===== Software Needed ===== | ||
| + | * [[adi> | ||
| + | * [[adi> | ||
| + | ===== Design and Integration Files ===== | ||
| + | * {{: | ||
| + | * {{: | ||
| + | ===== Equipment Needed ===== | ||
| + | * Analog signal source and antialiasing filter | ||
| + | * Sample clock source | ||
| + | * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[ads7-v2|ADS7-V2EBZ]]) | ||
| + | * PC running Windows® | ||
| + | * USB 2.0 port | ||
| + | * [[adi> | ||
| + | * [[ads7-v2|ADS7-V2EBZ]] FPGA-based data capture kit | ||
| + | ===== Getting Started ===== | ||
| + | This section provides quick start procedures for using the evaluation board for AD9680 or AD9234. \\ | ||
| + | |||
| + | ==== Configuring the Board ==== | ||
| + | Before using the software for testing, configure the evaluation board as follows: | ||
| + | - Connect the evaluation board to the [[ads7-v2|ADS7-V2EBZ]] data capture board, as shown in Figure 2. | ||
| + | - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[ads7-v2|ADS7-V2EBZ]] board. Connect the Standard-B USB port of the [[ads7-v2|ADS7-V2EBZ]] board to the PC with the supplied USB cable. | ||
| + | - Turn on the [[ads7-v2|ADS7-V2EBZ]]. | ||
| + | - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager as shown in Figure 3.{{ : | ||
| + | - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | ||
| + | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock. | ||
| + | - On the ADC evaluation board, provide a clean, low jitter clock source to connector J804 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:< | ||
| + | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
| + | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
| + | |||
| + | ==== Visual Analog Setup ==== | ||
| + | - Click Start < | ||
| + | - On the VisualAnalog “New Canvas” window, click **ADC**< | ||
| + | - At this point, VisualAnalog will automatically detect the evaluation board and the FPGA data capture board and ask if it can program the FPGA with the appropriate bin file. This is shown in figure 6. Programming the FPGA will provide power to the evaluation board. {{ : | ||
| + | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 7){{ : | ||
| + | - Click the **Settings** button in the **ADC Data Capture** block as shown in Figure 8 {{ : | ||
| + | - On the **General** tab make sure the clock frequency is set to the appropriate sample rate (eg. **1000MHz** or **500MHz**). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADs7-V2 FPGA software supports up to 2M FFT capture (1M per channel){{ : | ||
| + | - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked. | ||
| + | - Click **OK** | ||
| + | ==== SPIController Setup ==== | ||
| + | - Click Start < | ||
| + | - Select the appropriate configuration file when prompted. | ||
| + | - In the **Global** tab, under the **Generic Read/ | ||
| + | - Individual Channel control for **ADC A** and **ADC B** are done using the **Device Index Register (0x008)** in the Global tab.{{ : | ||
| + | - Under **ADC A** and **ADC B** tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with: | ||
| + | - **Chip Configuration Register (0x002)**: This option allows the channel to be powered on | ||
| + | - **Buffer Current Setting (0x018)**: This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, | ||
| + | - **Analog Input Differential Termination (0x016)**: This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, | ||
| + | - **Input Full Scale Range (0x025)**: At high input frequencies, | ||
| + | ===== Sample Configuration 1: Full Bandwidth Mode ===== | ||
| + | - Set the ADC Configuration Registers in **ADCBase0** tab. Write **Chip Mode Control Register** address 0x200 to **Full Bandwidth Mode** and **Chip Decimation Ratio Control Register** 0x201 to **Full Sample Rate**.{{ : | ||
| + | - For JESD204B setting, proceed to **ADCBase3** tab. Check the **Serial Transmit Power Down** box in **JESD204B Link Control Register (0x571)**.{{ : | ||
| + | - Set the Lane Rate setting register 0x56E to **Maximum Lane Rate**. The decision to use **Maximum Lane Rate** mode or **Low Lane Rate** mode should be based on the Lane Line Rate that was calculated in [[/ | ||
| + | - Set the **JESD204B Quick Configuration register (0x570)**. For 1000MSPS operation with **NO** DDCs (//Full Bandwidth Mode//), the values for **L.M.F** are **4.2.1**{{ : | ||
| + | - Proceed to **ADCBase4** tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.{{ : | ||
| + | - On address **0x58F**, change the Converter Resolution to **14** for AD9680 (12 for AD9234). | ||
| + | - Back to **ADCBase3** tab, uncheck the **Serial Transmit Power Down** box in JESD204B Link Control Register (0x571). | ||
| + | - After the quick configuration setting is completed, the **PLL Lock Detect register 0x56F** will read **0x80** to denote a lock. The SPIController interface will show a " | ||
| + | ==== Obtaining an FFT ==== | ||
| + | - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 18.{{ : | ||
| + | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) | ||
| + | - To save the FFT plot do the following | ||
| + | - Click on the Float Form button in the FFT window{{ : | ||
| + | - Click on File < | ||
| + | |||
| + | ===== Sample Configuration 2: Two ADCs Plus Two DDCs, Decimate by 4 ===== | ||
| + | - In the VisualAnalog Setup, follow Steps 1-5 and after that, click the **ADC Data Capture Settings**, remove **Ch.A and Ch.B** output data, and add **Ch. DDC0 and Ch. DDC1** output data.{{ : | ||
| + | - In the SPIController Setup, follow Steps 1-4. | ||
| + | - Set the ADC Configuration Registers in **ADCBase0** tab. Write **Chip Mode Control Register (0x200)** to **Two Digital Down Converters** and **Chip Decimation Ratio Control Register (0x201)** to **Decimate by 4**.{{ : | ||
| + | - For DDC settings, proceed to **ADCBase1** tab and configure DDC0 and DDC1 Control Registers with corresponding addresses of **0x310** and **0x330**, respectively, | ||
| + | - For frequency tuning word (FTW), addresses **0x314-315** are set as required by application for DDC0, and addresses **0x334-335** are set as required by application for DDC1. Figure xx below shows the calculation for NCO Frequency Tuning Word. {{ : | ||
| + | - After setting all DDC registers, go to **Generic Write/ | ||
| + | - For JESD204B setting, proceed to **ADCBase3** tab. Check the **Serial Transmit Power Down** box in **JESD204B Link Control Register (0x571)**.{{ : | ||
| + | - Set the Lane Rate setting register 0x56E to **Maximum Lane Rate**. The decision to use **Maximum Lane Rate** mode or **Low Lane Rate** mode should be based on the Lane Line Rate that was calculated in [[/ | ||
| + | - Set the **JESD204B Quick Configuration register (0x570)**. For 1000MSPS operation with **2** DDCs (//Two Digital Down Converters// | ||
| + | - Proceed to **ADCBase4** tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.{{ : | ||
| + | - On address **0x58F**, change the Converter Resolution to **14** for AD9680 (12 for AD9234). | ||
| + | - Back to **ADCBase3** tab, uncheck the **Serial Transmit Power Down** box in JESD204B Link Control Register (0x571). | ||
| + | - After the quick configuration setting is completed, the **PLL Lock Detect register 0x56F** will read **0x80** to denote a lock. The SPIController interface will show a " | ||
| + | |||
| + | ==== Obtaining an FFT ==== | ||
| + | - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 32.{{ : | ||
| + | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) | ||
| + | ===== Validating Deterministic Latency Using Subclass 1 Operation ===== | ||
| + | The following .zip files contain the files needed for users to validate subclass 1 operation and observe the latency | ||
| + | {{: | ||
| + | {{: | ||
| + | |||
| + | |||
| + | ===== Troubleshooting Tips ===== | ||
| + | ** FFT plot appears abnormal ** | ||
| + | * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. | ||
| + | * In VisualAnalog, | ||
| + | * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure 33{{ : | ||
| + | |||
| + | ** The FFT plot appears normal, but performance is poor. ** | ||
| + | * Make sure you are using the appropriate band-pass filter on the analog input. | ||
| + | * Make sure the signal generators for the clock and the analog input are clean (low phase noise). | ||
| + | * If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies. | ||
| + | * Make sure the SPI config file matches the product being evaluated. | ||
| + | |||
| + | ** The FFT window remains blank after the Run button is clicked ** | ||
| + | * Make sure the evaluation board is securely connected to the ADS7-V2. | ||
| + | * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the ADS7-V2. | ||
| + | * Make sure the correct FPGA //bin// file was used to program the FPGA. | ||
| + | * Be sure that the correct sample rate is programmed. Click on the **Settings** button in the **ADC Data Capture** block in VisualAnalog, | ||
| + | * Ensure that the REFCLOCK is ON and set to the appropriate frequency. | ||
| + | * Restart SPIController. | ||
| + | |||
| + | ** VisualAnalog indicates that the “FIFO capture timed out” or "FIFO not ready for read back" ** | ||
| + | * Make sure all power and USB connections are secure. | ||
| + | * Make sure that the REFCLOCK is ON and set to the appropriate frequency. | ||
| + | |||
| + | ** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ||
| + | * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure 35.{{ : | ||
| + | * Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. This can be done using SPIController. | ||
resources/eval/ad9680-1000ebz.txt · Last modified: 05 Feb 2024 03:49 by Deferson Romero