Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revisionBoth sides next revision
resources:eval:ad9645-125ebz_ad9635-125ebz [24 Aug 2012 01:56] – ready to approve Doug Itoresources:eval:ad9645-125ebz_ad9635-125ebz [02 Nov 2012 01:08] – edit Pin Mode Section Doug Ito
Line 106: Line 106:
 ===== Modes of Operation ===== ===== Modes of Operation =====
 ==== Standalone (PIN) Mode ==== ==== Standalone (PIN) Mode ====
-The [[adi>AD9645|AD9645]]/[[adi>AD9635|AD9635]] ADCs can operate in pin mode if there is no need to program and change the default modes of operation via the SPI. For applications that do not require SPI mode operation, the CSB pin is tied to DRVDD by connecting J301 Pin 6 to Pin 9. In this configuration the SDIO/PDWN pin controls the power-down function, and the SCLK/DFS pin controls the digital output format. +The [[adi>AD9645|AD9645]]/[[adi>AD9635|AD9635]] ADCs can operate in pin mode if there is no need to program and change the default modes of operation via the SPI. For applications that do not require SPI mode operation, the CSB pin is tied to DRVDD by removing the J301 jumper that connects Pin 6 to Pin 9. In this configuration the SDIO/PDWN pin controls the power-down function, and the SCLK/DFS pin controls the digital output format. 
 Table 2 and Table 3 specify the settings for pin mode operation. Table 2 and Table 3 specify the settings for pin mode operation.
  
 == Table 2. Power Down Mode Pin Settings == == Table 2. Power Down Mode Pin Settings ==
-^SDIO/PDWN Pin Voltage   ^Device Mode            |+^SDIO/PDWN (J301 Pin 2) Voltage   ^Device Mode            |
 |DRVDD    |Power Down Device| |DRVDD    |Power Down Device|
 |AGND  |Run Device, Normal Operation| |AGND  |Run Device, Normal Operation|
  
 == Table 3. Digital Output Format Pin Settings == == Table 3. Digital Output Format Pin Settings ==
-^SCLK/DFS Voltage         ^Output Format|+^SCLK/DFS (J301 Pin 5) Voltage         ^Output Format|
 |AGND    |Offset Binary          | |AGND    |Offset Binary          |
 |DRVDD                 |Twos Complement                   | |DRVDD                 |Twos Complement                   |
resources/eval/ad9645-125ebz_ad9635-125ebz.txt · Last modified: 09 Jan 2021 00:22 by Robin Getz

Page Tools