The AD9577 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9577. The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLLs have I2C programmable output frequency/format and an array of physical control pins that can be turned on and off on the evaluation board.
The AD9577s four differential outputs can be driven by an on board 25MHz crystal or through an SMA connector. The output differential transmission line pairs use 50Ω single ended characteristic impedance and are connected to standard edge launch SMA connectors. The AD9577 evaluation board uses RoHS-compliant FR-4 material. For convenience, detailed information from the AD9577 data sheet has been included here. Use this user guide in conjunction with the AD9577 data sheet and software documentation available at www.analog.com.
The following instructions are for setting up the physical connections to the AD9577-EVALZ evaluation board. The user must install the evaluation software prior to connecting the evaluation board for the first time.
Refer to the Evaluation Board Software section for details on running the AD9577 evaluation board software.
Use the following instructions to set up the AD9577 evaluation board software.
Do not connect the evaluation board until the software installation is complete.
Power up and connect the evaluation board to the PC. See the Evaluation Board Hardware section for details on the various connectors on the evaluation board. At start up, the graphical user interface (GUI) displays the dialog shown in Figure 2. The software allows the user to work online with an evaluation board or to work offline without an evaluation board. When working offline, the user can adjust all of the AD9577 settings and create configuration files for later use when an evaluation board is available.
When Run In Online Mode is selected, the main panel is displayed as in Figure 3. The title bar displays “Online Mode”. Most of the interface is disabled until I2C communication is verified by clicking the Check Connection button in the upper-left corner.
After clicking Check Connection and I2C communication is working, the GUI panel is fully enabled and loaded with the default values for the part. The software is now ready to change the AD9577 settings and features such as output frequencies, output formats, and spread spectrum settings. The fully enabled Main Window is shown in Figure 4 in the Evaluation Software Components section of this user guide.
When Run In Offline Mode is selected, the panel loads with default values and all controls enabled except the Acquire button. The title bar displays “Offline Mode”. The same controls are available as in online mode; however, they do not actually perform any I2C writes. The Check Connection button is also not present. Offline mode can be used to generate a setup file, which can be later used in Online Mode. See the Evaluation Software Components section for a description of the evaluation software features.
To create a setup file:
Many controls are active only under certain conditions. Input pin states and power switches determine which controls are active. Active controls are displayed with a white background, while inactive controls have a grey background as shown in Figure 5.
Unlike many Windows programs, inactive controls can still be edited and still cause the registers to be changed in the AD9577 (in Online mode). This is to support applications where the part configuration may be switched dynamically (such as when MARGIN or REFSEL are controlled by a microcontroller).
Certain combinations of values can cause the AD9577 operating parameters to exceed the valid ranges as specified in the datasheet. In some of these cases, the GUI will highlight invalid values in red.
The following conditions are checked within the software:
Figure 6 shows the result when several invalid values have been selected. The invalid values and the constraints that have been violated are highlighted in red. Note that there may be additional requirements specified on the datasheet that are not validated by the user interface.
The input pin controls are located in the lower-left corner of the GUI (Figure 7). The software controls only affect the appearance of the GUI. To change the state of these pins, you must adjust the jumpers on the evaluation board. Setting the input pin controls to match the evaluation board setup allows the proper controls to be displayed as active. Table 1 outlines each input pin and the corresponding section that it appears in within this user guide.
|Input Pin Name||Section Within User Guide|
|REFSEL||Input Frequency Section|
|MARGIN||PLL and Output Divider Section|
|SSCG||Spread Spectrum Section|
|MAXBW||Please Refer to the AD9577 Datasheet|
Table 1. Input Pin Name and Corresponding User Guide Section
The input frequency section of the Main Window is used to identify which input reference (XO or REFCLK) is being used and the frequency of that reference. By default, REFSEL is set to High and the input frequency section will look like the left side of Figure 8. The XO Frequency drop-down is used to select which frequency of crystal oscillator is connected to the AD9577. When REFSEL control is set to Low, the panel will look like the right hand side of Figure 8.
The external REFCLK frequency being used should be typed into the text box under REFCLK Frequency (MHz). The software expects that a reference clock between 19.44MHz and 27MHz is externally given to the AD9577 when REFCLK divider=1 is used. If any other value outside of this range is entered into REFCLK frequency, the software will turn controls red to signify that the REFCLK frequency is too high. It is possible to apply a reference frequency between 38.88MHz and 54MHz if REFCLK divider is set to 2.
When the REFCLK divider=1 the REFCLK is applied directly to both PLLs. When REFCLK divider=2 the REFCLK is divided by two before being applied to both PLLs. It is important to remove the jumper that shorts the REFCLK input to ground (P11) when the REFCLK is in use. It is also important to know that the CMOS REFCLK output of the AD9577 will be a copy of the applied REFCLK and not the divided down REFCLK.
The PLL and Output Divider Section of the Main Window shown in Figure 9 is used to set the various divider values in both of the AD9577 PLLs. This section also calculates output frequency based on the reference frequency and divider values entered by the user. Selecting Margin equal to High or Low in the Input Pins Control causes the selected Margin setting to illuminate. By default, MARGIN is low and only the top central section (labeled “If MARGIN pin is set LOW”) is active. The other section can be edited, but it will not have any effect on the operation of the AD9577 until the MARGIN pin jumper (P8) is adjusted.
The top half of each group contains the PLL1 controls. PLL1 is an integer-N PLL and the VCO1 frequency is the product of the input frequency and the feedback divider. PLL2 powers up as an integer-N PLL but it is possible to use it as a Frac-N PLL. In Integer-N mode, VCO2 frequency is calculated the same as VCO1 frequency. When PLL2 is run in fractional-N PLL mode, the effective feedback divider is adjusted by the fractional word and the modulus registers as described in the equation below.
To set PLL2 to fractional-N mode, the BLEED & SDM switch shown in Figure 10 must be turned on. When it is turned off, the FRAC and MOD boxes are grayed out.
It is important to note that the PLL1 and PLL2 feedback dividers should not be set equal to each other. This could cause reduced performance due to injection locking between the two VCOs. The output frequencies are calculated by dividing the VCO frequency by the product of the corresponding VCO Divides and Output Divider.
The Margin pin can be switched from low to high by adjusting the MARGIN Jumper on the evaluation board (P8). It is a good idea if you are using PLL2 as a Frac-N PLL when MARGIN is high that PLL2 is also being used as a Frac-N PLL when MARGIN is low. Figure 11 shows how the PLL and Output Divider Section changes when MARGIN is switched to High within the software.
The Output Format and SYNC section allows the user to adjust the PLL1 or PLL2 output formats and SYNC settings. Figure 9 shows the Output Format and SYNC section of the Main Window. To change which output format is used, select the desired format from the dropdown menu. Table 2 shows the possible output formats supported by the AD9577. The format is specified as OUT1/OUT0 or OUT3/OUT2.
Table 2. Supported Output Formats
*all four CMOS ouputs per PLL are in phase
Changing output format only adjusts the output drivers of the AD9577. The LVPECL termination resistors need to be removed for LVDS or CMOS operation. It is important to note that it is not possible to have different output formats for the different states of the MARGIN pin.
When the SYNC check boxes are selected, the display will appear as shown in Figure 13. The VCO Divider boxes for OUT1 and OUT3 become shaded because when SYNC is checked, OUT0/OUT1 share a VCO divider and OUT2/OUT3 share a VCO divider. It is important to note that when SYNC is checked, the sync occurs for both states of the MARGIN PIN.
This section of the GUI panel allows the user to turn sections of the AD9577 off and on. There are on and off switches for the following: PLL1, PLL2, CH0 Output, CH1 Output, CH2 Output, CH3 Output, and the REFOUT output. When each switch is turned off, the GUI display also updates to indicate which controls will not have any effect. For example, if PLL1 and CH3 are both turned off, the display will look like Figure 14, indicating that only OUT2 will have a signal.
The Spread Spectrum Section can be illuminated in the Main Window by changing SSCG to High in the Input Pins Control Section. The right side of Figure 15 shows the illuminated section.
Spread spectrum mode is physically enabled on PLL2 by adjusting the SSCG Jumper (P7) on the evaluation board such that the SSCG pin is high. PLL2 must be in Fractional-N mode for spread spectrum operation to function. The output frequency is modulated with a triangular profile and the peak power is reduced. The tri-wave modulation is implemented by controlling the divide ratio of the feedback divider. This is achieved by ramping the fractional word to the SDM.
The key parameters that define the frequency modulation profile are:
The following equations determine the value of the above parameters:
The following are programmable registers that affect the previous equations:
The default values for FracStep, NumStep, and CkDiv are all 0 and must be modified before spread-spectrum operation will function.
The Acquire button in the Main Window forces the AD9577 to perform a new acquisition. The Reset button resets the AD9577 back to its default power up state. After a reset, the feedback dividers, VCO dividers, output dividers, output format, output sync, SSCG registers and on/off switches are all returned to their default settings. Figure 16 shows the Acquire and Reset buttons.
Figure 16. Acquire and Reset Buttons
The File menu has the following options:
Selecting Reset to Default resets the AD9577 to its default power-up state. This is the same as the Reset DUT button in the Main Window.
Selecting Open Setup reads a setup (.stp) file and applies the saved register settings to the AD9577. A setup file is a text file that contains the AD9577 register settings.
Selecting Save Setup writes a setup (.stp) file containing all of the register settings currently loaded in the AD9577.
This selection is only valid after performing one of the previous two actions. This sets the registers of the AD9577 back to the last opened or saved configuration.
Selecting Export JSON creates a file used for automatic programming in certain applications. This is not typically used.
Exits the evaluation software. No checking is performed to ensure that the existing setup is saved.
The Help Menu only contains the About section which shows the a short summary of the software being used.