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resources:eval:ad9574-user-guide [27 Apr 2015 15:46] – [Quick Start Guide] Kyle Slightomresources:eval:ad9574-user-guide [05 Feb 2021 22:58] (current) – [Signal Connections] Petre Minciunescu
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 ===== General Description ===== ===== General Description =====
 ---- ----
-The [[adi>AD9574|AD9574]] evaluation board is a compact, easy-to-use platform for evaluating all features of the [[adi>AD9574|AD9574]]. The [[adi>AD9574|AD9574]] provides a multiple output clock generator function compromising of a dedicated PLL core optimized for Ethernet and gigabit line card applications. Configuring the [[adi>AD9574|AD9574]] for a particular application requires only the connection of external pull-up or pull-down resistors to the appropriate pin program reader pins (PPRx). These pins provide control of the internal dividers for establishing the desired frequency translations, clock output functionality, and input reference functionality. Connecting an external 19.44 MHz or 25 MHz oscillator to one or both of the REF0_P/REF0_N or REF1_P/REF1_N reference inputs results in a set of output frequencies prescribed by the PPRx pins. Connecting a stable clock source (8 kHz/10 MHz/19.44 MHz/25 MHz/38.88 MHz) to the monitor clock input enables the optional monitor circuit providing quality of service (QoS) status for REF0 or REF1. +The [[adi>AD9574|AD9574]] evaluation board is a compact, easy-to-use platform for evaluating all features of the [[adi>AD9574|AD9574]]. The [[adi>AD9574|AD9574]] provides a multiple output clock generator function comprising of a dedicated PLL core optimized for Ethernet and gigabit line card applications. Configuring the [[adi>AD9574|AD9574]] for a particular application requires only the connection of external pull-up or pull-down resistors to the appropriate pin program reader pins (PPRx). These pins provide control of the internal dividers for establishing the desired frequency translations, clock output functionality, and input reference functionality. Connecting an external 19.44 MHz or 25 MHz oscillator to one or both of the REF0_P/REF0_N or REF1_P/REF1_N reference inputs results in a set of output frequencies prescribed by the PPRx pins. Connecting a stable clock source (8 kHz/10 MHz/19.44 MHz/25 MHz/38.88 MHz) to the monitor clock input enables the optional monitor circuit providing quality of service (QoS) status for REF0 or REF1. 
  
 <WRAP centeralign> <WRAP centeralign>
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 ==== Power Connections ====  ==== Power Connections ==== 
-Connect the included 6V wall supply to P500 to power all of the necessary on board components.  Ensure the P501 jumper is connected between pins 1 and 2 and P502 is connected between pins 1 and 2.  Alternatively, the user may remove the jumper at P502 and connect an external 3.3V supply to pin 2.+Connect the included 6V wall supply to P500 to power all of the necessary on board components.  Ensure the P501 jumper is connected between pins 1 and 2 and P502 is connected between pins 1 and 2.  Alternatively, the user may remove the jumper at P502 and connect an external 3.3V supply to pin 2 and pin 3 (GND).
 ==== Signal Connections ==== ==== Signal Connections ====
 === Reference Inputs (REFx) === === Reference Inputs (REFx) ===
-The AD9574/PCBZ allows for the reference inputs to be clocked by one of two crystal oscillators (XO) at Y202 and Y204 or via single ended SMA connectors J215 and J217.  The default signal path is to use 25MHz CMOS XOs for both REF0_P and REF1_P.\\+The AD9574/PCBZ allows for the reference inputs to be clocked by one of two crystal oscillators (XO) at Y202 and Y204 or via single ended SMA connectors J217 and J215.  The default signal path is to use 25MHz CMOS XOs for both REF0_P and REF1_P.\\
 \\ \\
 The following board modifications from the default BOM are required to use the SMA reference input connectors to supply a differential reference instead of the 25MHz XOs: The following board modifications from the default BOM are required to use the SMA reference input connectors to supply a differential reference instead of the 25MHz XOs:
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 The following board modifications from the default BOM are required to use the SMA reference input connectors to supply an external single ended CMOS reference input instead of the 25MHz XOs: The following board modifications from the default BOM are required to use the SMA reference input connectors to supply an external single ended CMOS reference input instead of the 25MHz XOs:
  - Remove R214, R217, R218, R221, R224, R225, T201 and T202  - Remove R214, R217, R218, R221, R224, R225, T201 and T202
- - Place R212, R219, C221 and C222 with 0Ω resistors.+ - Place R212, R219, C221, C222, C226, and C227 with 0Ω resistors.
 \\ \\
 +<note important>Although the AD9574 evaluation board has the footprint for two crystal resonators Y201 and Y203, the AD9574 is not specified to work with crystal resonators and their usage in conjunction with the AD9574 is not recommended</note>
 +
 + 
 === Monitor Clock Input (MCLK_x) === === Monitor Clock Input (MCLK_x) ===
 The AD9574/PCBZ provides a signal path to the MCLK_x inputs using SMA connector J216.  The default BOM configuration allows for a 3.3V single ended CMOS signal to be applied to SMA connector J216 with the monitor clock input set to differential using the PPR6 biasing jumpers. The AD9574/PCBZ provides a signal path to the MCLK_x inputs using SMA connector J216.  The default BOM configuration allows for a 3.3V single ended CMOS signal to be applied to SMA connector J216 with the monitor clock input set to differential using the PPR6 biasing jumpers.
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 |PPR3              |P414-P416                          |OUT4_x and OUT5_x configurations               |  |PPR3              |P414-P416                          |OUT4_x and OUT5_x configurations               | 
 |PPR4              |P418-P420                          |OUT6_x configuration                           | |PPR4              |P418-P420                          |OUT6_x configuration                           |
-|PPR5              |P422-P424                          |Reference frequency monitor error threshold  | +|PPR5              |P422-P424                          |Reference clock frequency monitor error threshold  | 
 |PPR6              |P426-P428                          |Monitor clock (MCLK) input configuration     |   |PPR6              |P426-P428                          |Monitor clock (MCLK) input configuration     |  
    
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 |REFMON         |P102   |Reference monitor disable |Reference monitor enable  | |REFMON         |P102   |Reference monitor disable |Reference monitor enable  |
  
 +==== Status LEDs ==== 
 +There are 5 status LEDs: 
 +  * DS102 reflects the state of REF_SW output pin: high when a reference switch is in progress 
 +  * DS103 reflects the state of REF_ACT output pin: low when REF0 is the active reference and high when REF1 is the active reference 
 +  * DS104 reflects the state of REF_FHI output pin: high when the reference frequency is above the upper threshold limit 
 +  * DS105 reflects the state of REF_FLO output pin: high when the reference frequency is below the lower threshold limit 
 +  * DS106 reflects the state of LD output pin: low when the PLL is unlocked and high when the PLL is locked
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
 ---- ----
-The quick start section covers simple PLL operation to lock the AD9574 PLL and output two high speed sample clocks and two SYSREF signals. See the AD9528 data sheet and Evaluation Software Components section for a detailed explanation of the various AD9528 features.+The quick start section covers simple PLL operation to lock the [[adi>AD9574|AD9574]] PLL and output various frequencies on OUT0 through OUT6. See the [[adi>AD9574|AD9574]] datasheet for a detailed explanation of the various [[adi>AD9574|AD9574]] features.
  
-Table 2 describes a summary of one possible operating mode of the AD9528 which is setup used for this quick start guide.+**Table 4** describes a summary of one possible operating mode of the [[adi>AD9574|AD9574]] which is setup used for this quick start guide.
  
-**Table 2. Quick Start Summary**+**Table 4. Quick Start Summary**
 ^ Parameter                           ^  Value             ^ ^ Parameter                           ^  Value             ^
 | Input Frequency and Logic Type      |  25MHz, 3.3V CMOS  | | Input Frequency and Logic Type      |  25MHz, 3.3V CMOS  |
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 | Reference Doubler Enable/Disable    |  Disable           | | Reference Doubler Enable/Disable    |  Disable           |
 | Reference Monitor Threshold         |  +/- 50ppm         | | Reference Monitor Threshold         |  +/- 50ppm         |
-| MCLK Input Frequency and Logic Type |  10MHz CMOS        |+| MCLK Input Frequency and Logic Type |  10MHz 3.3V CMOS   |
 | Reference Doubler Enable/Disable    |  Disable           | | Reference Doubler Enable/Disable    |  Disable           |
-| OUT0 Frequency and Logic Type       | 25MHz CMOS        | +| OUT0 Frequency and Logic Type       | 25MHz 3.3V CMOS   | 
-| OUT1 Frequency and Logic Type       | 25MHz CMOS        |+| OUT1 Frequency and Logic Type       | 25MHz 3.3V CMOS   |
 | OUT2 Frequency and Logic Type       | 156.25MHz HSTL    | | OUT2 Frequency and Logic Type       | 156.25MHz HSTL    |
 | OUT3 Frequency and Logic Type       | 156.25MHz HSTL    | | OUT3 Frequency and Logic Type       | 156.25MHz HSTL    |
 | OUT4 Frequency and Logic Type       | 100MHz HSTL       | | OUT4 Frequency and Logic Type       | 100MHz HSTL       |
 | OUT5 Frequency and Logic Type       | 125MHz HSTL       | | OUT5 Frequency and Logic Type       | 125MHz HSTL       |
-| OUT6 Frequency and Logic Type       | 33.33MHz CMOS     |+| OUT6 Frequency and Logic Type       | 33.33MHz 3.3V CMOS|
  
-Use the following steps to lock the AD9574 PLL to the on board 25MHz XO and output the frequencies listed in **Table 3**.  +Use the following steps to lock the AD9574 PLL to the on board 25MHz XO and output the frequencies listed in **Table 4**.  
   - Connect the 6V wall supply to P500 with jumpers P501 and P502 set to short pins 1 and 2.   - Connect the 6V wall supply to P500 with jumpers P501 and P502 set to short pins 1 and 2.
   - Connect a 10MHz 3.3V CMOS signal to J216   - Connect a 10MHz 3.3V CMOS signal to J216
-  - Set the following PPRx states: +  - Set the following PPRx states using the jumpers outlines in **Table 1**: 
-    - PPR0: State 0 +      * PPR0: State 0 
-    - PPR1: State 0 +      * PPR1: State 0 
-    - PPR2: State 3 +      * PPR2: State 3 
-    - PPR3: State 0 +      * PPR3: State 0 
-    - PPR4: State 7 +      * PPR4: State 7 
-    - PPR5: State 4 +      * PPR5: State 4 
-    - PPR6: State 6 +      * PPR6: State 6 
  
-As long as all jumpers have remained in their default positions, the AD9574 should now be operational. A red LED on the left side of the board, just below the round electrolytic capacitors, should now be illuminated, indicating that the AD9574 is now in a locked condition.+The <fc #FF0000>red</fc> LED labeled DS106 is connected to the LD pin through a buffer and should be illuminated indicating that the AD9574 is now in a locked condition.
resources/eval/ad9574-user-guide.1430142417.txt.gz · Last modified: 27 Apr 2015 15:46 by Kyle Slightom

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