This user guide describes specific functionality of the AD9528 evaluation board hardware and evaluation board software. General software features including software installation instructions are covered in the Clock Generation and Distribution Evaluation Software User Guide. The AD9528 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9528 JESD204B Clock Generator. The AD9528 is a dual loop jitter cleaner and clock generator with internal SYSREF generator compliant with JEDEC JESD204B for multi-device synchronization. The AD9528 can output up to 14 clock signals, with any output configurable to PLL1direct out, PLL2, or SYSREF. 8 total outputs, 2 reference inputs, and a SYSREF input are accessible on the evaluation board. The AD9528/PCBZ has a fully configurable power supply to allow the user to evaluate the AD9528 while being powered directly by buck regulators or external LDOs. Use this user guide in conjunction with the AD9528 data sheet and software documentation available at www.analog.com.
The following instructions are for setting up the physical connections to the AD9528/PCBZ. The user must install the evaluation software prior to connecting the evaluation board to their PC.
The AD9528/PCBZ is setup by default to power the AD9528 and remaining circuitry using the provided 6V wall power supply connected to drive an Analog Devices ADP5052 5-channel integrated power solution which is configured to output 3.3V and 5V from two internal buck regulators. The evaluation board can be configured to power the AD9528 with one of three on board power configurations as shown in Table 1.
Table 1. Power Supply Configuration Jumper Settings
|Jumper P9||Jumper P10||Jumper P11|
|3.3V LDO powered by 5V buck converter output (Default)||Set to position 1 (Enable)||Set to position 1 (LDO)||Set to position 1 (Filter)|
|3.3V Buck Converter Output Through Passive Filter Network||Set to position 3 (Disable)||Set to position 3 (Switcher)||Set to position 1 (Filter)|
|3.3V Buck Converter Output Direct||Set to position 3 (Disable)||Set to position 1 (LDO)||Set to position 3 (Switcher)|
The following instructions assume that the power supply is correctly configured to one of the three configurations discussed in the Power Connections section.
Refer to the Evaluation Board Software section for details on running the AD9528 evaluation board software.
The AD9528/PCBZ has preinstalled connections for REFA, REFB, VCXO_IN, SYSREF_IN, and SYSREF_REQ. REFA and REFB are accessible via SMA connectors J27 and J4. A 0dBm sinusoidal input may be connected to these inputs to provide a reference signal to PLL1 of the AD9528. The AD9528 can create an internally generated SYSREF signal or can provide a buffered external SYSREF by applying signals to SYSREF_IN via SMA connectors J6 and J7. A third SYSREF option allows an external trigger to initiate SYSREF pulse from the internal SYSREF generator. The SYSREF_REQ pin is accessible by 3 paths on the evaluation board:
A low phase noise VCXO with single ended 3.3V CMOS output is populated by default. The AD9528/PCBZ allows the user to use an external VCXO evaluation daughter board by utilizing J14 which is connected to the AD9528 VCXO_VT pin and J101 which can be shorted to the AD9528 VCXO_IN_P pin. The path connected to J101 can also be used to provide a reference to PLL with an external 3.3V CMOS source. A third path allows the AD9528 to be configured as an asynchronous generator by using a small 3.3V CMOS XO on Y1. The following steps detail how to configure the AD9528/PCBZ for the three different VCXO_IN input options:
Connect an oscilloscope, spectrum analyzer, or other lab equipment to any of the horizontal OUTx inputs on the edge of the board. OUT0, OUT1, OUT11, and OUT12 are differentially terminated with 100Ω and ac coupled to SMA connectors J10-J13 and J34-J37. OUT4, OUT5, OUT8, and OUT9 are differentially terminated with 100Ω and combined to one output via a balun to SMA connectors J18, J20, J26 and J29. Baluns T8 and T13 can be removed and shorted so that both the positive and negative outputs from OUT4 and OUT9 can be connected to SMA connectors.
The AD9528 evaluation software allows the user to control the full functionality of the AD9528 through SPI communication on the evaluation board and a fully interactive software GUI. Please see the Clock Generation and Distribution Evaluation Software User Guide for general information on installing and running the software including software features that are redundant across multiple Clock and Distribution products.
The AD9528 evaluation software allows the user to control the full functionality of the AD9528 through SPI communication on the evaluation board. This section will detail device specific features of the AD9528 evaluation software. Generic software functionality is covered in the Clock Generation and Distribution Evaluation Software User Guide.
The quick start section covers only simple PLL operation to lock both AD9528 PLLs and output two high speed sample clocks and two SYSREF signals. See the AD9528 data sheet and Evaluation Software Components section for a detailed explanation of the various AD9528 features.
Table 2 describes a summary of one possible operating mode of the AD9528 which is setup used for this quick start guide.
Table 2. Quick Start Summary
|Input Frequency||122.88MHz on REFA|
|Output Frequency||122.88MHz on OUT0 and 245.75MHz on OUT10|
|SYSREF Frequency||960kHz on OUT1 and OUT11|
|SYSREF Type||Internally generated 4 Pulse N-Shot|
|PLL1 Reference Divider||4|
|PLL1 Phase Detector Frequency||30.72MHz|
|PLL1 External VCXO Frequency||122.88MHz|
|PLL1 Feedback Divider (N Divider)||4|
|PLL2 Phase Detector Frequency||122.88MHz|
|PLL2 VCO Frequency||3686.4MHz|
|PLL2 Feedback Divider (N Divider)||10|
|PLL2 VCO Divider (M Divider)||3|
|Output Divider||10 on OUT0 and 5 on OUT10|
Use the following steps to configure and lock both AD9528 PLLs by loading a premade setup file.