Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий
This version is outdated by a newer approved version.DiffThis version (13 Feb 2013 19:12) is a draft.
Approvals: 0/1

This is an old revision of the document!

Table of Contents

GENERAL DESCRIPTION

The AD9525 evaluation board is a compact, easy to use platform for evaluating all features of the AD9508. Two versions of the evaluation board are available : one with a prepopulated external VCO and loop filter (AD9525/PCBZ-VCO) and one with no VCO/VCXO and no loop filter (AD9525/PCBZ). This user guide focuses on the AD9525/PCBZ-VCO, which already has a VCO and loop filter on board. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be used with an external VCO or VCXO. The VCO input and eight LVPECL outputs can operate up to a frequency of 3.6 GHz. All outputs share a common divider that can provide a division of 1 to 6. The AD9525 also offers a dedicated output that can be used to provide a programmable signal for resetting or synchronizing a data converter. For more information about the device, see the AD9525 data sheet. This user guide should be used in conjunction with the AD9525 data sheet and the software documentation available at www.analog.com/clocks


Figure 1. AD9525/PCBZ-VCO

FEATURES

  • Simple power connection using 6 V wall adapter and on board LDO voltage regulators
  • 6 ac-coupled differential LVPECL SMA connectors
  • 2 single-ended LVPECL SMA connectors
  • 1 LVPECL or 2 CMOS SMA connectors for sync output
  • SMA connectors for:
    • 3 reference inputs
    • Charge pump output
    • Clock distribution input
  • USB connection to PC
  • Microsoft Windows-based evaluation software with simple graphical user interface (supports 64-bit versions of Windows)
  • On-board PLL loop filter
  • Easy access to digital I/O and diagnostic signals via I/O header
  • Status LEDs for diagnostic signals

APPLICATIONS

  • LTE and multicarrier GSM base stations
  • Clocking high speed ADCs, DACs
  • ATE and high performance instrumentation
  • 40 Gbps/100 Gbps OTN line side clocking
  • Cable/DOCSIS CMTS clocking
  • Test and measurement











EVALUATION BOARD HARDWARE

The instructions in this section are for setting up the physical connections to the AD9525/PCBZ-VCO evaluation board with a prepopulated VCO. There is another version of the evaluation board (AD9525/PCBZ) that does not contain an external VCO. The two variations of the evaluation boards have slightly different default configurations.

When connecting the evaluation board to a PC for the first time, you must install the evaluation software prior to connecting the evaluation board. If a previous version of the software is already installed, uninstall it before installing the latest version.

Power and PC Connections

  1. Install the AD9525 evaluation software, uninstall prior versions of the software before installation updates. Administrative privileges are required for installation. The 64-bit versions of Windows® are supported.
  2. Connect the 6V wall power supply to the main power connector labeled P500.
  3. Connect the USB cable to the evaluation board and the computer. The red LED labeled CR400 on the AD9525 evaluation board should illuminate.
  4. If the Found New Hardware Wizard window automatically appears when the evaluation board is connected, select Install the software automatically and click Next. The Found New Hardware Wizard window may appear twice, and a system restart may be required.

Refer to the Evaluation Board Software section for details on running the AD9525 evaluation board software.

Signal Connections

To connect signals:

  1. Connect a signal generator to the J202 (REF A) SMA connector or to the J204 (REF B) SMA connector. By default, the reference inputs on this evaluation board are ac-coupled and terminated 50 Ω to ground. An amplitude setting of 0 dBm to 6 dBm is sufficient.
  2. Connect an oscilloscope, spectrum analyzer, or other lab equipment to any of the J301 to J316 SMA clock OUT connectors on the edge of the board.
    1. OUT0 through OUT7 are ac-coupled LVPECL outputs terminated 150 Ω to ground.
    2. OUT3 and OUT6 contain a balun for differential to single-ended conversion. Connector J317 and J318 are for the SYNC_OUT distribution and are also ac-coupled LVPECL outputs terminated 150 Ω to ground.
    3. SYNC_OUT can be configured as two single-ended CMOS outputs, in which case each line should be terminated with a series resistor.

Bypassing the PLL (Clock Distribution Only)

To bypass the PLL:

  1. Connect a signal generator to the SMA connector labeled CLKIN.
  2. Remove C215.
  3. Install a 0 Ω resistor or ac coupling capacitor at R218. By default, this path contains a 6 dB T-type attenuator in between Connector J206 and the CLKIN pin.

The AD9525 default register settings configure the device as an eight output clock buffer.

Using An OFF-Board VCO/VCXO

To use an off-board VCO or VCXO:

  1. Remove the original VCO/VCXO or disconnect all supply voltages. (You may see coupling between the VCO/VCXO paths if two VCO/VCXOs are powered at the same time, causing pulling.)
  2. Install a 0 Ω resistor at R217 and remove R225.
  3. Connect the external VCO/VCXO voltage tune input to J200 (CP_OUTPUT).
  4. Remove C215 and install a 0 Ω resistor or ac coupling capacitor at R218.
  5. Connect the off-board VCO/VCXO output to the J206 SMA connector (CLKIN).
  6. Design and populate a loop filter for the desired loop bandwidth and phase margin.

Note that the right angle SMA connectors on the evaluation board are not optimal for high speed signals. They are provided for ease of use but may cause loss of performance at speeds greater than 1.5 GHz.

LOOP FILTER DESIGN

The AD9525 PLL requires an external VCO or VCXO and a loop filter containing components tailored for a given application. The third-order passive configuration shown in Figure 2 usually results in the best performance for many applications and is the one found on the evaluation board.


Figure 2. PLL Loop Filter

resources/eval/ad9525-user-guide.1360779136.txt.gz · Last modified: 13 Feb 2013 19:12 by Kyle Slightom

Page Tools