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resources:eval:ad9257-65ebz_ad9637-80ebz [26 Nov 2012 21:19] – [Troubleshooting Tips] Bud Samiljan | resources:eval:ad9257-65ebz_ad9637-80ebz [08 Jan 2021 10:50] (current) – Fixed bad link for AD9257 Ioana Chelaru | ||
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+ | ====== EVALUATING THE AD9257/ | ||
+ | ===== Preface ===== | ||
+ | This user guide describes the [[adi> | ||
+ | \\ | ||
+ | \\ | ||
+ | Though the information on this page applies generally to the currently released version of the AD9257-65EBZ and AD9637-80EBZ, | ||
+ | \\ | ||
+ | \\ | ||
+ | The [[adi> | ||
+ | |||
+ | ===== Typical Measurement Setup ===== | ||
+ | {{ : | ||
+ | <WRAP centeralign> | ||
+ | //Figure 1. Evaluation Board Connection—[[adi> | ||
+ | </ | ||
+ | |||
+ | ===== Features ===== | ||
+ | * Full featured evaluation board for the [[adi> | ||
+ | * SPI interface for setup and control | ||
+ | * External, on-board oscillator, or [[adi> | ||
+ | * Balun/ | ||
+ | * On-board LDO regulator or switching regulator, needing a single external 6V, 2A dc supply | ||
+ | * VisualAnalog® and SPI controller software interfaces | ||
+ | |||
+ | ===== Helpful Documents ===== | ||
+ | * [[adi> | ||
+ | * High speed ADC FIFO evaluation kit ([[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | |||
+ | |||
+ | ===== Design and Integration Files ===== | ||
+ | * [[adi> | ||
+ | ===== Equipment Needed ===== | ||
+ | * Analog signal source and antialiasing filter | ||
+ | * Sample clock source (if not using the on-board oscillator) | ||
+ | * Two switching power supplies (6.0V, 2.5A), CUI EPS060250UH-PHP-SZ provided | ||
+ | * PC running Windows® | ||
+ | * USB 2.0 port | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | |||
+ | ===== Getting Started ===== | ||
+ | This section provides quick start procedures for using the [[adi> | ||
+ | |||
+ | ==== Configuring the Board ==== | ||
+ | Before using the software for testing, configure the evaluation board as follows: | ||
+ | - Connect the evaluation board to the data capture board, as shown in Figure 1. | ||
+ | - Connect one 6V, 2.5A switching power supply (such as the CUI, Inc., EPS060250UH-PHP-SZ that is supplied) to the [[adi> | ||
+ | - Connect one 6V, 2.5A switching power supply (such as the supplied CUI EPS060250UH-PHP-SZ) to the [[adi> | ||
+ | - Connect the [[adi> | ||
+ | - On the ADC evaluation board, confirm that the jumpers are installed as shown in Figure 2. | ||
+ | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal to the desired channel(s). Use a shielded, RG-58, 50Ω coaxial cable (optimally 1 m or shorter) to connect the signal generator. For best results, use a narrow-band, | ||
+ | |||
+ | ===== Evaluation Board Hardware ===== | ||
+ | The evaluation board provides the support circuitry required to operate the [[adi> | ||
+ | \\ | ||
+ | See [[adi> | ||
+ | |||
+ | ==== Power Supplies ==== | ||
+ | This evaluation board comes with a wall-mountable switching power supply that provides a 6V, 2A maximum output. Connect the supply to a 100V ac to 240V ac, 47Hz to 63Hz wall outlet. The output from the supply is provided through a 2.1mm inner diameter jack that connects to the printed circuit board (PCB) at P101. The 6V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators that supply the proper bias to each of the various sections on the board.\\ | ||
+ | \\ | ||
+ | The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove the E101, E102, E104, E105, E111, E112, E113, E114, E115 and E116 ferrite beads to disconnect the bench supply traces from the on-board LDOs. Note that in some board configurations some of these might already be uninstalled. P102 and P103 need to be installed to connect external bench supplies to the board. E106, E107, E108 and E109 need to be populated to connect P102 and P103 to the board power domains. A 1.8V , 0.5A supply is needed for 1.8V_DUT_AVDD and 1.8V_DRVDD. Although the voltage requirements are the same for 1.8V_DUT_AVDD and 1.8V_DRVDD, it is recommended that separate supplies be used for each of these.\\ | ||
+ | \\ | ||
+ | Two additional supplies, 5.0V_AVDD and 3.3V_AVDD, are used to bias the optional input path amplifiers and optional [[adi> | ||
+ | |||
+ | ==== Input Signals ==== | ||
+ | When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or an equivalent. Use a shielded, RG-58, 50Ω coaxial cable (optimally 1 m or shorter) for connecting to the evaluation board. Enter the desired frequency and amplitude (see the Specifications section in the data sheet of the respective part). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50Ω terminations is recommended. Analog Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters directly to the evaluation board.\\ | ||
+ | \\ | ||
+ | If an external clock source is used, it should also be supplied with a clean signal generator as previously specified for the analog input signals. Analog Devices evaluation boards typically can accept ~2.8V p-p or 13 dBm sine wave input for the clock. If an external off-board clock source is used, remove the jumper on P601, and C1109, to disable and disconnect the on-board crystal oscillator. | ||
+ | |||
+ | ==== Output Signals ==== | ||
+ | The default setup uses the Analog Devices high speed converter evaluation platform ([[adi> | ||
+ | |||
+ | ===== Jumper Settings ===== | ||
+ | Set the jumper settings/ | ||
+ | \\ | ||
+ | == Table 1. Jumper Settings == | ||
+ | ^Jumper | ||
+ | |J203 |Use this jumper to power down the ADC. Using the SPI, the PDWN pin can be configured to be STBY (standby).| | ||
+ | |J1001 and J1002 | ||
+ | |J301 |This jumper sets the ADC for SPI communications with the [[adi> | ||
+ | |J1103 | ||
+ | |J202 |This jumper selects between internal V< | ||
+ | |P1201 | ||
+ | \\ | ||
+ | {{ : | ||
+ | <WRAP centeralign> | ||
+ | //Figure 2. Default Jumper Connections for [[adi> | ||
+ | </ | ||
+ | |||
+ | ===== Evaluation Board Circuitry ===== | ||
+ | This section explains the default and optional ADC settings or modes allowed on the [[adi> | ||
+ | \\ | ||
+ | ==== Power ==== | ||
+ | Connect the switching power supply that is supplied in the evaluation kit between a rated 100V ac to 240V ac, 47Hz to 63Hz wall outlet and P101.\\ | ||
+ | \\ | ||
+ | ==== Analog Input ==== | ||
+ | The eight channel inputs on the evaluation board are set up for a double balun-coupled analog input with a 50Ω impedance. The default analog input configuration supports analog input frequencies of up to ~200 MHz.\\ | ||
+ | \\ | ||
+ | ==== RBIAS ==== | ||
+ | RBIAS has a default setting of 10 kΩ (R205) to ground and is used to set the ADC core bias current. Note that using a resistor value other than a 10kΩ, 1% resistor for RBIAS may degrade the performance of the device.\\ | ||
+ | \\ | ||
+ | ==== Clock ==== | ||
+ | The default clock input circuit is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T1101) that adds a low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sinusoidal inputs. The transformer converts the single-ended input to a differential signal that is clipped by CR1101 before entering the ADC clock inputs. The [[adi> | ||
+ | \\ | ||
+ | The [[adi> | ||
+ | |||
+ | ===== Modes of Operation ===== | ||
+ | ==== Standalone (PIN) Mode ==== | ||
+ | The [[adi> | ||
+ | Table 2 and Table 3 specify the settings for pin mode operation. | ||
+ | |||
+ | == Table 2. Digital Output Format Pin Settings == | ||
+ | ^SDIO/DFS (J301 Pin 2) Voltage | ||
+ | |1.8V_DUT_AVDD (jumper J301 Pin 2 to Pin 3) |Twos Complement| | ||
+ | |GND (" | ||
+ | |||
+ | == Table 3. Digital Test Pattern Pin Settings == | ||
+ | ^SCLK/DTP (J301 Pin 5) Voltage | ||
+ | |GND (" | ||
+ | |1.8V_DUT_AVDD (jumper J301 Pin 5 to Pin 6) |10 0000 0000 0000 | | ||
+ | |||
+ | Note that the above settings only apply when CSB is tied high (J301 Pin 8 " | ||
+ | |||
+ | Additional information on the Standalone (PIN) Mode is provided in the [[adi> | ||
+ | ==== Default Mode ==== | ||
+ | To operate the device under test (DUT) using the SPI, follow the jumper settings for J301 as shown in Table 1. | ||
+ | |||
+ | ===== How To Use The Software For Testing ===== | ||
+ | ==== Setting up the ADC Data Capture ==== | ||
+ | After configuring the board, set up the ADC data capture using the following steps: | ||
+ | - Open VisualAnalog on the connected PC. The appropriate part type should be listed in the status bar of the **VisualAnalog – New Canvas** window. Select the template that corresponds to the type of testing to be performed (see Figure 3, where the [[adi> | ||
+ | - After the template is selected, a message might appear asking if the default configuration can be used to program the FPGA (see Figure 4). If this message appears, click **Yes**, and the window closes.\\ {{ : | ||
+ | - To change features to settings other than the default settings, click the **Expand Display** button, located on the bottom right corner of the window (see Figure 5), to see what is shown in Figure 6.\\ | ||
+ | - Change the features and capture settings by consulting the detailed instructions in the [[adi> | ||
+ | <WRAP centeralign>// | ||
+ | \\ | ||
+ | \\ | ||
+ | \\ | ||
+ | </ | ||
+ | <WRAP centeralign>// | ||
+ | |||
+ | ===== Evaluation And Test ===== | ||
+ | ==== Setting up the SPI Controller Software ==== | ||
+ | After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure: | ||
+ | - Open the SPI controller software by going to the **Start** menu or by double-clicking the **SPIController** software desktop icon. If prompted for a configuration file, select the appropriate one. If not, check the title bar of the window to determine which configuration is loaded. If necessary, choose **Cfg Open** from the **File** menu and select the appropriate file based on your part type. Note that the **CHIP ID(1)** box should be filled to indicate whether the correct SPI controller configuration file is loaded (see Figure 7).{{ : | ||
+ | - Click the **New DUT** button in the **SPIController** window (see Figure 8){{ : | ||
+ | - In the **ADCBase 0** tab of the **SPIController** window, find the **CLOCK DIVIDE(B)** box (see Figure 9), and the **MODES(8)** box (see Figure 10). If using the clock divider, use the drop-down box to select the correct clock divide ratio, if necessary. If there is any interruption of the ADC clock during power-up or during operation, a Digital Reset may be needed to re-initialize the ADC (Figure 10). For additional information, | ||
+ | - Note that other settings can be changed on the **ADCBase 0 tab** (see Figure 9) and the **ADC A** through **ADC H** tabs (see Figure 11) to set up the part in the desired mode. The **ADCBase 0** tab settings affect the entire part, whereas the settings on the **ADC A** through **ADC H** tabs each affect the selected channel only. See the appropriate part data sheet, the [[adi> | ||
+ | - Click the **Run** or **Continuous Run** button in the **VisualAnalog** toolbar (see Figure 12).{{ : | ||
+ | |||
+ | ==== Adjusting the Amplitude of the Input Signal ==== | ||
+ | The next step is to adjust the amplitude of the input signal for each channel as follows: | ||
+ | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. Examine the **Fund Power** reading in the left panel of the **VisualAnalog Graph - AD9257 FFT** window (see Figure 13).{{ : | ||
+ | - Repeat this procedure for the other channels, if desired | ||
+ | - Click the floppy-disk icon within the **VisualAnalog Graph - AD9257 FFT** window to save the performance data as a .csv formatted file for plotting or analysis. | ||
+ | ===== Troubleshooting Tips ===== | ||
+ | Lack of SPI communication will cause difficulty in configuring the ADC. | ||
+ | * Go to the **Global** tab of the **SPIController** window and push the **Read** button in the **GENERIC READ/ | ||
+ | * Check that there is correct power to the [[adi> | ||
+ | * Check that the USB cable is properly connected from the PC to the [[adi> | ||
+ | * The LED on the **VisualAnalog ADCDataCapture** block should be green. If it is red, push the USB button on the same block to refresh the connection.\\ | ||
+ | |||
+ | If the FFT plot appears abnormal, do the following: | ||
+ | * If you see an abnormal noise floor, go to the **ADCBase0** tab of the **SPIController** window and toggle the **Chip Power Mode** in **MODES(8)** from **Chip Run** to **Reset** and back. | ||
+ | * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure that you are not overdriving the ADC. Reduce the input level, if necessary. | ||
+ | * In **VisualAnalog**, | ||
+ | |||
+ | If the FFT appears normal but the performance is poor, check the following: | ||
+ | * Make sure that an appropriate filter is used on the analog input. | ||
+ | * Make sure that the signal generators for the clock and the analog input are clean (low phase noise). | ||
+ | * Change the analog input frequency slightly if noncoherent sampling is being used. | ||
+ | * Make sure that the SPI configuration file matches the product being evaluated.\\ | ||
+ | |||
+ | If the FFT window remains blank after **Run** in VisualAnalog (see Figure 12) is clicked, do the following: | ||
+ | * Make sure that the evaluation board is securely connected to the [[adi> | ||
+ | * Make sure that the FPGA has been programmed by verifying that the **DONE** LED is illuminated on the [[adi> | ||
+ | * Make sure that the correct FPGA program was installed by clicking the **Settings** icon in the **ADC Data Capture** block in VisualAnalog. Then select the **FPGA** tab and verify that the proper FPGA bin file is selected for the part.\\ | ||
+ | |||
+ | If VisualAnalog indicates that the **FIFO Capture timed out**, do the following: | ||
+ | * Make sure that all power and USB connections are secure. | ||
+ | * Probe the DCO signal at P802 (Pin A10 and/or Pin B10) on the evaluation board, and confirm that a clock signal is present at the ADC sampling rate. |