Wiki

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
Next revision Both sides next revision
resources:eval:ad6684-500ebz [05 May 2017 16:26]
JudyChui [Visual Analog Setup]
resources:eval:ad6684-500ebz [05 May 2017 17:08]
JudyChui [Obtaining an FFT - NSR Mode]
Line 65: Line 65:
   - On the VisualAnalog “New Canvas” window, select the desired AD9694 canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD6684 in the same chip operating mode with the same decimation rate. If Pair AB is in NSR mode then Pair CD must also be in NSR mode.  If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ :​resources:​eval:​newcanvas.jpg?​nolink |}}<WRAP centeralign>//​Selecting the [[adi>​AD6684|AD6684]] canvas //</​WRAP>​   - On the VisualAnalog “New Canvas” window, select the desired AD9694 canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD6684 in the same chip operating mode with the same decimation rate. If Pair AB is in NSR mode then Pair CD must also be in NSR mode.  If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ :​resources:​eval:​newcanvas.jpg?​nolink |}}<WRAP centeralign>//​Selecting the [[adi>​AD6684|AD6684]] canvas //</​WRAP>​
   - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ :​resources:​eval:​9694_program_FPGA.png?​nolink |}}<WRAP centeralign>//​Programming the [[ads7-v2|ADS7-V2EBZ]]//</​WRAP>​   - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ :​resources:​eval:​9694_program_FPGA.png?​nolink |}}<WRAP centeralign>//​Programming the [[ads7-v2|ADS7-V2EBZ]]//</​WRAP>​
-  - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to 2x the input clock. For example, if the input clock to the AD6684 is 368.64 MHz then set the **Clock Frequency (MHz)** to 737.28 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel). Select the desired DDC output pair(s) using the "​select data" pull down menu. {{ :​resources:​eval:​ddcdatacapturesetting.jpg?nolink |}}<WRAP centeralign>//​Changing the ADC Capture Settings//</​WRAP>​+  - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to 2x the input clock. For example, if the input clock to the AD6684 is 368.64 MHz then set the **Clock Frequency (MHz)** to 737.28 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel). {{ :​resources:​eval:​9694_data_capture_settings_general.png?nolink |}} <WRAP centeralign>//​Changing the ADC Capture Settings//</​WRAP>​
   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :​resources:​eval:​fig4_expand_display.png?​nolink |}}<WRAP centeralign>//​Expanding Display in VA//</​WRAP>​   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :​resources:​eval:​fig4_expand_display.png?​nolink |}}<WRAP centeralign>//​Expanding Display in VA//</​WRAP>​
   - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked.   - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked.
Line 87: Line 87:
     - The **Memory Map View** can be accessed from the AD6684 **Device View**. ​ The **Memory Map View** can be used to individually write registers in the AD6684. ​ **Note: When writing individual registers it is imperative to first write the Pair Index register (0x0009) before any other write so that the correct ADC channel pair (Pair AB or Pair CD) is being addressed. ​ If writing a local register, subsequently write the ADC channel index register (0x0008) so that the desired channel within the desired pair is written (Channel A/C or Channel B/D).** {{ :​resources:​eval:​6684_ace_memorymap_view.png?​nolink |}}<WRAP centeralign>//​Memory Map View//</​WRAP>​     - The **Memory Map View** can be accessed from the AD6684 **Device View**. ​ The **Memory Map View** can be used to individually write registers in the AD6684. ​ **Note: When writing individual registers it is imperative to first write the Pair Index register (0x0009) before any other write so that the correct ADC channel pair (Pair AB or Pair CD) is being addressed. ​ If writing a local register, subsequently write the ADC channel index register (0x0008) so that the desired channel within the desired pair is written (Channel A/C or Channel B/D).** {{ :​resources:​eval:​6684_ace_memorymap_view.png?​nolink |}}<WRAP centeralign>//​Memory Map View//</​WRAP>​
 ==== Obtaining an FFT - NSR Mode ==== ==== Obtaining an FFT - NSR Mode ====
-  - Using the AD6684_Quad_Normal_FFT.vac canvas file, the first item to configure in Visual Analog is the input clock frequency. ​ This needs to be set to twice the frequency of the input clock. ​ Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.{{ :​resources:​eval:​9694_data_capture_settings_general.png?​nolink |}}<WRAP centeralign>//​AD6684 FFT Data Capture Settings//</​WRAP>​+  - The first item to configure in Visual Analog is the input clock frequency. ​ This needs to be set to twice the frequency of the input clock. ​ Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.{{ :​resources:​eval:​9694_data_capture_settings_general.png?​nolink |}}<WRAP centeralign>//​AD6684 FFT Data Capture Settings//</​WRAP>​
   - In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. ​ Click on the settings button on the FFT Analysis block and configure the settings in Visual Analog to match the NSR settings that have been programmed into the AD6684. Under Advanced Calculation,​ click the Enable box, select AD6674 NSR, and then select the appropriate bandwidth mode and tuning word.  Make sure to set the Bandwidth to match the mode.  When finished, click the Apply button and then the OK button to apply the settings. {{ :​resources:​eval:​6684_va_fftanalysis_nsr.png?​nolink |}}<WRAP centeralign>//​AD6684 FFT Analysis NSR Settings//</​WRAP>​   - In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. ​ Click on the settings button on the FFT Analysis block and configure the settings in Visual Analog to match the NSR settings that have been programmed into the AD6684. Under Advanced Calculation,​ click the Enable box, select AD6674 NSR, and then select the appropriate bandwidth mode and tuning word.  Make sure to set the Bandwidth to match the mode.  When finished, click the Apply button and then the OK button to apply the settings. {{ :​resources:​eval:​6684_va_fftanalysis_nsr.png?​nolink |}}<WRAP centeralign>//​AD6684 FFT Analysis NSR Settings//</​WRAP>​
   - In this example, with an input clock of 368.64MHz, the output sample rate is 368.64MSPS. ​ The default JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.2.2 (L.M.F). ​ The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "​Configuring the Board"​). ​   - In this example, with an input clock of 368.64MHz, the output sample rate is 368.64MSPS. ​ The default JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.2.2 (L.M.F). ​ The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "​Configuring the Board"​). ​
Line 99: Line 99:
     - The VDR mode (complex/​real),​ bandwidth (25%/43%), and tuning word can be configured from the **Device View** in ACE.  VDR defaults to 25% bandwidth complex mode with a tuning word of 0. In this example a real input signal is used so the tuning word and mode must be changed. ​ See the AD6674 data sheet for more details on the available bandwidth modes and tuning words. To access the device view, double-click the **AD6684** icon from the **AD6684 Eval Board** view which will bring up the view below. In this example VDR is set to **Dual Real 25% BW Mode** with the tuning word set to 6. Once the settings have been entered click **Apply Changes** in the upper left of the **Device View**. ​ This will apply changes to the ADC Pair (Pair AB or Pair CD) selected in the **Device View**. ​ To do so, set the **ADC Pair Selection** to the desired pair, configure the block diagram as desired and click **Apply Changes** in the upper left of the window. ​ This should be done for each pair (Pair AB and Pair CD). {{ :​resources:​eval:​6684_ace_device_view_vdr.png?​nolink |}}<WRAP centeralign>//​Pair AB: Channel A and Channel B VDR Settings//</​WRAP>​     - The VDR mode (complex/​real),​ bandwidth (25%/43%), and tuning word can be configured from the **Device View** in ACE.  VDR defaults to 25% bandwidth complex mode with a tuning word of 0. In this example a real input signal is used so the tuning word and mode must be changed. ​ See the AD6674 data sheet for more details on the available bandwidth modes and tuning words. To access the device view, double-click the **AD6684** icon from the **AD6684 Eval Board** view which will bring up the view below. In this example VDR is set to **Dual Real 25% BW Mode** with the tuning word set to 6. Once the settings have been entered click **Apply Changes** in the upper left of the **Device View**. ​ This will apply changes to the ADC Pair (Pair AB or Pair CD) selected in the **Device View**. ​ To do so, set the **ADC Pair Selection** to the desired pair, configure the block diagram as desired and click **Apply Changes** in the upper left of the window. ​ This should be done for each pair (Pair AB and Pair CD). {{ :​resources:​eval:​6684_ace_device_view_vdr.png?​nolink |}}<WRAP centeralign>//​Pair AB: Channel A and Channel B VDR Settings//</​WRAP>​
 ==== Obtaining an FFT - VDR Mode ==== ==== Obtaining an FFT - VDR Mode ====
-  - Using the AD6684_Quad_Normal_FFT.vac canvas file, the first item to configure in Visual Analog is the input clock frequency. ​ This needs to be set to twice the frequency of the input clock. ​ Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.{{ :​resources:​eval:​9694_data_capture_settings_general.png?​nolink |}}<WRAP centeralign>//​AD6684 FFT Data Capture Settings//</​WRAP>​+  - The first item to configure in Visual Analog is the input clock frequency. ​ This needs to be set to twice the frequency of the input clock. ​ Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.{{ :​resources:​eval:​9694_data_capture_settings_general.png?​nolink |}}<WRAP centeralign>//​AD6684 FFT Data Capture Settings//</​WRAP>​
   - In this example, with an input clock of 368.64MHz, the output sample rate is 368.64MSPS. ​ The default JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.2.2 (L.M.F). ​ The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "​Configuring the Board"​). ​   - In this example, with an input clock of 368.64MHz, the output sample rate is 368.64MSPS. ​ The default JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.2.2 (L.M.F). ​ The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "​Configuring the Board"​). ​
   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :​resources:​eval:​6684_vdr_fft_tw6_fin150mhz.png?​800 |}}<WRAP centeralign>//​AD6684 FFT with VDR Enabled (Tuning Word = 6//</​WRAP>​   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :​resources:​eval:​6684_vdr_fft_tw6_fin150mhz.png?​800 |}}<WRAP centeralign>//​AD6684 FFT with VDR Enabled (Tuning Word = 6//</​WRAP>​
Line 112: Line 112:
     - When making changes to the DDC settings the **DDC Soft Reset** must be written afterwards. ​ To do so, select **DDC Held in Reset** from the drop down menu in the block diagram. ​ Then click **Apply Changes** in the upper left of the AD6684 Device view in ACE.  Next, select **Normal Operation** from the drop down menu in the block diagram and then click **Apply Changes** once again. ​ This process resets the DDC and then places the DDC back into normal operating mode.  This must be done for each pair (Pair AB and/or Pair CD) for which DDC changes have been applied. {{ :​resources:​eval:​6684_ace_device_view_1ddc_complexinout_ddc_softreset.png?​nolink |}}<WRAP centeralign>//​Pair AB: Channel A and Channel B DDC0 Settings with DDC Soft Reset//</​WRAP>​     - When making changes to the DDC settings the **DDC Soft Reset** must be written afterwards. ​ To do so, select **DDC Held in Reset** from the drop down menu in the block diagram. ​ Then click **Apply Changes** in the upper left of the AD6684 Device view in ACE.  Next, select **Normal Operation** from the drop down menu in the block diagram and then click **Apply Changes** once again. ​ This process resets the DDC and then places the DDC back into normal operating mode.  This must be done for each pair (Pair AB and/or Pair CD) for which DDC changes have been applied. {{ :​resources:​eval:​6684_ace_device_view_1ddc_complexinout_ddc_softreset.png?​nolink |}}<WRAP centeralign>//​Pair AB: Channel A and Channel B DDC0 Settings with DDC Soft Reset//</​WRAP>​
 ==== Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode ==== ==== Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode ====
-  - On the VisualAnalog “New Canvas” window, click **Existing** and select the desired canvas. ​ There are three canvas options currently available. ​ Select the canvas when operating one DDC per pair of ADC channels (**AD6684_Quad_2DDC_FFT.vac**). **Note: Pair AB is in complex DDC0 mode with a decimation rate of 2 and pair CD must also be in complex DDC0 mode with a decimation rate of 2.**{{ :​resources:​eval:​6684_va_newcanvas_existing_2ddc.png?​nolink |}}<WRAP centeralign>//​Selecting the [[adi>​AD6684|AD6684]] canvas //</​WRAP>​ +  - The first item to configure in Visual Analog is the input clock frequency. ​ This needs to be set to twice the frequency of the input clock. ​ Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog. ​ Also, make sure that the output data is set to *Ch. DDC0 Data*.{{ :​resources:​eval:​6684_data_capture_settings_ddc0.png?​nolink |}}<WRAP centeralign>//​AD6684 FFT Data Capture Settings//</​WRAP>​
-  - Using the AD6684_Quad_2DDC_FFT.vac canvas file, the first item to configure in Visual Analog is the input clock frequency. ​ This needs to be set to twice the frequency of the input clock. ​ Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog. ​ Also, make sure that the output data is set to *Ch. DDC0 Data*.{{ :​resources:​eval:​6684_data_capture_settings_ddc0.png?​nolink |}}<WRAP centeralign>//​AD6684 FFT Data Capture Settings//</​WRAP>​+
   - In this example, with an input clock of 368.64MHz, the output sample rate is 184.32MSPS. ​ The  JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.4.4 (L.M.F). ​ The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "​Configuring the Board"​). ​   - In this example, with an input clock of 368.64MHz, the output sample rate is 184.32MSPS. ​ The  JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.4.4 (L.M.F). ​ The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "​Configuring the Board"​). ​
   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :​resources:​eval:​6684_2ddc_complex_inout_ncopassthrough_fft_fin345p1mhz.png?​800 |}}<WRAP centeralign>//​AD6684 FFT with DDC0 Enabled//</​WRAP>​   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :​resources:​eval:​6684_2ddc_complex_inout_ncopassthrough_fft_fin345p1mhz.png?​800 |}}<WRAP centeralign>//​AD6684 FFT with DDC0 Enabled//</​WRAP>​
resources/eval/ad6684-500ebz.txt · Last modified: 28 Feb 2019 16:54 by ayu3