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EVALUATING THE AD6679 IF DIVERSITY RECEIVER

Preface

This user guide describes the AD6679 evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described. The HSC-ADC-EVALEZ is the recommended FPGA based data capture board for the AD6679. The ADS7-V2EBZ may alternatively be used as the FPGA based data capture board for the AD6679.

The AD6679 data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to highspeed.converters@analog.com.

AD6679 Evaluation Board

Figure 1. AD6679 Evaluation Board

Typical Measurement Setup

Figure 2. Evaluation Board Connection—AD6679-500EBZ (on Left) and HSC-ADC-EVALEZ (on Right)

Features

  • Full featured evaluation board for the AD6679
  • SPI interface for setup and control
  • Wide band Balun driven input
  • No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC
  • VisualAnalog® and SPI controller software interfaces

Helpful Documents

Software Needed

Design and Integration Files

Equipment Needed

  • Analog signal source and antialiasing filter
  • Sample clock source
  • 12V, 6.5A switching power supply (supplied with the HSC-ADC-EVALEZ or the SL POWER CENB1080A1251F01 supplied with ADS7-V2EBZ)
  • PC running Windows®
  • USB 2.0 port
  • HSC-ADC-EVALEZ FPGA-base data capture kit
  • ADS7-V2EBZ FPGA-based data capture kit (optional, but not required - if an ADS7-V2EBZ has been previously purchased for use with other ADI ADCs then it may be also be used for the AD6679-500EBZ)

Getting Started

This section provides quick start procedures for using the evaluation board for AD6679.

Configuring the Board

Before using the software for testing, configure the evaluation board as follows:

  1. Connect the evaluation board to the HSC-ADC-EVALEZ data capture board, as shown in Figure 2.
  2. Connect one 12V, 6.5A switching power supply to P1301 on the HSC-ADC-EVALEZ board. Connect the Standard-B USB port of the HSC-ADC-EVALEZ board to the PC with the supplied USB cable.
  3. The HSC-ADC-EVALEZ will appear in the Device Manager as shown in Figure 3.

    Figure 3. Device Manager showing HSC-ADC-EVALEZ

  4. If the Device Manager does not show the HSC-ADC-EVALEZ listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1.
  5. On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock.
  6. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
  7. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)

Visual Analog Setup

  1. Click Start right All Programs right Analog Devices right VisualAnalog right VisualAnalog
  2. On the VisualAnalog “New Canvas” window, click ADCrightDualrightAD6679

    Figure 4. Selecting the AD6679 canvas

  3. If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5)

    Figure 5. Expanding Display in VA

  4. Click the Settings button in the ADC Data Capture block as shown in Figure 6

    Figure 6. Changing the ADC Capture Settings

  5. On the General tab make sure the clock frequency is set to 500MHz (or other clock frequency). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The HSC-ADC-EVALEZ FPGA software supports up to 2M FFT capture (1M per channel)

    Figure 7. Setting the clock frequency and Capture length

  6. Click on the Capture Board tab and browse to the ad9684_evalez_05202014_0903am.mcs file. Click the Program button. The FPGA_DONE LED should illuminate on the HSC-ADC-EVALEZ board indicating that the FPGA has been correctly programmed. The bin file is available at the ftp site ftp://ftp.analog.com/pub/HSC_ADC_Apps/AD9684CE01A_Design_Support/ad9684_evalez_05202014_0903am.mcs
  7. Click OK

SPIController Setup

  1. Click Start right All Programs right Analog Devices right SPIController right SPIController
  2. Select the appropriate configuration file when prompted.
  3. In the Global tab, under the Generic Read/Write section, write 0x81 to register 0x000. This issues a Soft reset for the DUT.

    Figure 8. Sending a Soft Reset to the AD6679

  4. Individual Channel control for ADC A and ADC B are done using the Device Index Register (0x008) in the Global tab.

    Figure 9. Device Index for ADC Channel A and Channel B

  5. Under ADC A and ADC B tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with:
    1. Chip Configuration Register (2): This option allows the channel to be powered on
    2. Buffer Current Setting (18): This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, the buffer current may need to be increased to optimize harmonic distortion performance (HD2, HD3). Keep in mind that at high frequencies, the performance is also jitter limited. So increasing the buffer currents may lead to diminishing returns with higher power consumption. Refer to the datasheet to understand the relationship between IAVDD3 and Buffer Current Setting.
    3. Analog Input Differential Termination (16): This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, but the analog input signal amplitude will be reduced.
    4. Input Full Scale Range (25): At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC.

Device Setup - NSR Mode

  1. The default Chip Application Mode for the AD6679-500 is set to NSR.

    Figure 10. Default Application Mode - NSR/Decimation by 2

  2. The NSR mode settings are configured in the ADCA and ADCB tabs. The NSR defaults to 21% bandwidth mode with a tuning word of 0.

    Figure 11. Channel A and Channel B NSR Settings

Obtaining an FFT - NSR Mode

  1. The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.

    Figure 12. AD6679-500 FFT Data Capture Settings

  2. In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. Click on the settings button on the FFT Analysis block and configure the settings in Visual Analog to match the NSR settings that have been programmed into the AD6679. Under Advanced Calculation, click the Enable box, select AD6679 NSR, and then select the appropriate bandwidth mode and tuning word. Make sure to set the Bandwidth to match the mode. When finished, click the Apply button and then the OK button to apply the settings.

    Figure 13. AD6679-500 FFT Analysis NSR Settings

  3. Click the Run button in Visual Analog and you should see the capture data similar to the plot below.

    Figure 14. AD6679-500 FFT with NSR Enabled

  4. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.) NSR imposes a ~3dB loss in the signal, but does not impact the dynamic range. A -1.0 dBFS input signal will show as -4.0 dBFS in the FFT in Visual Analog.
  5. To save the FFT plot do the following
    1. Click on the Float Form button in the FFT window

      Figure 15. Floating the FFT window

    2. Click on File right Save Form As button and save it to a location of choice

      Figure 16. Saving the FFT

Device Setup - VDR Mode

  1. The default Chip Application Mode for the AD6679 is set to NSR. The settings in the ADCBase0 tab must be changed to configure the AD6679 into VDR mode. To set up the AD6679 for VDR mode change the Chip Application Mode in register 0x200 to Variable Dynamic Range (VDR) Mode and set the Chip Decimation Ratio in register 0x201 to Full Sample Rate.

    Figure 17. Set Application Mode to VDR

  2. The VDR mode tuning word can be configured in the ADC A and ADC B tabs. VDR defaults to 25% bandwidth complex mode with a tuning word of 0. The tuning word can be changed using the VDR Tuner Frequency selection (register 0x434). See the AD6679 data sheet for more details on the available bandwidth modes and tuning words.

    Figure 18. Channel A and Channel B VDR Settings

Obtaining an FFT - VDR Mode

  1. The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.

    Figure 19. AD6679-500 FFT Data Capture Settings

  2. Click the Run button in Visual Analog and you should see the capture data similar to the plot below.

    Figure 20. AD6679-500 FFT with VDR Enabled

  3. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.) VDR imposes no loss on the input signal so a -1.0 dBFS input signal will show as -1.0 dBFS in the FFT in Visual Analog.
  4. To save the FFT plot do the following
    1. Click on the Float Form button in the FFT window

      Figure 21. Floating the FFT window

    2. Click on File right Save Form As button and save it to a location of choice

      Figure 22. Saving the FFT

Setting up SPIController to Output the VDR High/Low Resolution Bit or the VDR Punish Bit - VDR Mode

  1. To enable the VDR High/Low Resolution bit go to the ADCBase2 tab in SPIController. In the OUTPUT CTRL MODE REG(559) drop down select “VDR High/Low Resolution Bit”.

    Figure 26. SPIController ADCBase2 Settings for VDR High/Low Resolution Bit on Status Pins

  2. Alternatively, the VDR Punish Bit can be enabled. To enable this bit go to ADCBase2 in SPIController and in the OUTPUT CTRL MODE REG(559) drop down select “Fast Detect (FD) or VDR Punish Bit

    Figure 27. SPIController ADCBase2 Settings for VDR Punish Bit on Status Pins

Viewing the VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode

  1. The first step is to open a new Logic canvas in VisualAnalog. In the Logic canvas configure the Input Formatter to set the Resolution to 16 bits and the Alignment to 18 bits. This will create the space such that the VDR status bit can be visible in the Logic canvas.

    Figure 28. Input Formatter Settings for VDR Indicators in the Status Bit

  2. Next configure the Logic Analysis block for the data alignement. Set the High Bit to 17 and the low bit to 0. This will align the canvas such that the VDR status bit can be visible in the Logic canvas.

    Figure 29. Logic Analysis Settings for Bit Alignment

  3. Once a signal is input that will trigger VDR to operate the VDR high/low resolution bit can be seen in the Logic Canvas display. The VDR high/low resolution bit indicates that the resolution is ≤13 bits.

    Figure 30. Logic Canvas Display Showing VDR High/Low Resolution Bit

  4. When a signal is input that will trigger VDR then the VDR punish bit may alternatively be enabled. The VDR punish bit can be seen in the Logic Canvas display. The VDR punish bit indicates that resolution is ≤12 bits.

    Figure 31. Logic Canvas Display Showing VDR Punish Bit

Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2

  1. The default Chip Application Mode for the AD6679 is set to NSR. The settings in the ADCBase0 tab must be changed to configure the AD6679 to use the DDCs. In this example the AD6679 is set up to use two DDCs (one per ADC channel) with real outputs and a decimation ratio of two. Set the Chip Application Mode in register 0x200 to Two Digital Down Converters and select the Only Real (I) Selected checkbox. Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio.

    Figure 33. Set Application Mode to 2 DDCs Real Mode Decimate by 2

  2. The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated.
    1. The tuning step is equal to the output sample rate divided by 4096.
      1. tuning step = 500MSPS/4096 = 122070.3125
    2. The translation frequency is equal to the output sample rate divided by 4*(decimation ratio).
      1. translation frequency = 500MSPS/(4*2) = 62500000
    3. The DDC Phase Increment is equal to the translation frequency divided by the tuning step.
      1. DDC Phase Increment = 62500000/122070.3125 = 512
  3. Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Variable IF Mode, Decimate by 4 Filter Selection (when in real mode this actually sets the AD6679 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512
    1. After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300).

      Figure 34. Channel A and Channel B DDC Settings

Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2

  1. The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 and DDC1 are being used in the AD6679 so this must be selected under the ADC Data Capture Settings.

    Figure 35. AD6679-500 FFT Data Capture Settings

  2. Click the Run button in Visual Analog and you should see the capture data similar to the plot below.

    Figure 36. AD6679-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled

  3. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. A -1.0 dBFS input signal will show as -1.7 dBFS in the FFT in Visual Analog.
  4. To save the FFT plot do the following
    1. Click on the Float Form button in the FFT window

      Figure 37. Floating the FFT window

    2. Click on File right Save Form As button and save it to a location of choice

      Figure 38. Saving the FFT

Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2

  1. The default Chip Application Mode for the AD6679 is set to NSR. The settings in the ADCBase0 tab must be changed to configure the AD6679 to use the DDC. In this example the AD6679 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two. Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is NOT checked. Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio.

    Figure 39. Set Application Mode to 1 DDC Complex ZIF Mode Decimate by 2

  2. The DDC settings must be configured under DDCO CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B.
    1. After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300).

      Figure 40. DDC Settings for Complex ZIF Mode

Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2

  1. The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 is being used in the AD6679 so this must be selected under the ADC Data Capture Settings.

    Figure 41. AD6679-500 FFT Data Capture Settings

  2. In order to exclude the image frequency from the SFDR measurements, configure Visual Analog to remove the image from its calculations. This is done under the FFT Analysis settings. Under the User-Defined tab add a new row by clicking Add. Name it ‘Image’. Use a symbol such as the # and set the Freq to ‘-fund’. Set the Single-Side Band to 3 Bins and set it as ‘Spur, Exclude’. Once done, select the row, and then hit the Move Up button to place this new row just below the row with Fund.

    Figure 42. AD6679-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled

  3. Click the Run button in Visual Analog and you should see the capture data similar to the plot below.

    Figure 43. AD6679-500 FFT with 1 DDC in Complex ZIF Mode with Dec2 Enabled

  4. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. A -1dBFS input signal will show as -2dBFS in Visual Analog.
  5. To save the FFT plot do the following
    1. Click on the Float Form button in the FFT window

      Figure 44. Floating the FFT window

    2. Click on File right Save Form As button and save it to a location of choice

      Figure 45. Saving the FFT

Troubleshooting Tips

FFT plot appears abnormal

  • If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary.
  • In VisualAnalog, Click on the Settings button in the Input Formatter block. Check that Number Format is set to the correct encoding (twos compliment by default). Repeat for the other channel.
  • Issue a Data Path Soft Reset through SPIController Global tab as shown in Figure 46

    Figure 46. Issuing a data path soft reset through SPIController

The FFT plot appears normal, but performance is poor.

  • Make sure you are using the appropriate band-pass filter on the analog input.
  • Make sure the signal generators for the clock and the analog input are clean (low phase noise).
  • If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies.
  • Make sure the SPI config file matches the product being evaluated.

The FFT window remains blank after the Run button is clicked

  • Make sure the evaluation board is securely connected to the HSC-ADC-EVALEZ.
  • Make sure the FPGA has been programmed by verifying that the Config DONE LED is illuminated on the HSC-ADC-EVALEZ. If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the HSC-ADC-EVALEZ setup process.
  • Make sure the correct FPGA bin file was used to program the FPGA.
  • Be sure that the correct sample rate is programmed. Click on the Settings button in the ADC Data Capture block in VisualAnalog, and verify that the Clock Frequency is properly set.

    Figure 47. Setting the correct clock frequeency in VisualAnalog

  • Restart SPIController.

VisualAnalog indicates that the “FIFO capture timed out” or “FIFO not ready for read back”

  • Make sure all power and USB connections are secure.

VisualAnalog displays a blank FFT when the RUN button is clicked

  • Ensure that the clock to the ADC is supplied. Using SPIController ADCBase0 tab the status of the clock can be read out. See figure 48.

    Figure 48. Clock Detection Status Register

/srv/wiki.analog.com/data/pages/resources/eval/ad6679-500ebz.txt · Last modified: 01 Mar 2016 19:34 by J.Harris