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resources:eval:ad6674-1000ebz [03 Jun 2015 19:18] – [Visual Analog Setup] Jonathan Harrisresources:eval:ad6674-1000ebz [19 Aug 2015 17:38] – [Viewing the VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode] Jonathan Harris
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     - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:ad6674_fft_graph_saveformas.png?nolink |}}<WRAP centeralign>//Figure 27. Saving the FFT//</WRAP>     - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:ad6674_fft_graph_saveformas.png?nolink |}}<WRAP centeralign>//Figure 27. Saving the FFT//</WRAP>
 ==== Setting up SPIController to Use Control Bits as VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode ==== ==== Setting up SPIController to Use Control Bits as VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode ====
-  - The first step go to the ADCBase2 tab in SPIController to set up the control bits to select the VDR indicator bits.  In this example Control Bit 2 is set to VDR Punish Bit 1, Control Bit 1 is set to VDR Punish Bit 0, and Control Bit 0 is set to the VDR High/Low resolution bit.{{ :resources:eval:ad6674_spi_vdr_bits_adcbase2.png?nolink |}}<WRAP centeralign>//Figure 28. SPIController ADCBase2 Settings for VDR Indicators in the Control Bits//</WRAP>+  - The first step go to the ADCBase2 tab in SPIController to set up the control bits to select the VDR indicator bits.  In this example Control Bit 2 is set to VDR Punish Bit 1, Control Bit 1 is set to VDR Punish Bit 0, and Control Bit 0 is set to the VDR High/Low resolution bit. (Similarly, the control bits may be set up to function as Overrange, Signal Monitor (SMON),  or Fast Detect (FD) indicators.){{ :resources:eval:ad6674_spi_vdr_bits_adcbase2.png?nolink |}}<WRAP centeralign>//Figure 28. SPIController ADCBase2 Settings for VDR Indicators in the Control Bits//</WRAP>
   - Next go to the ADCBase4 tab to set up the control bits to select the VDR indicator bits.  In this example three control bits are sent per sample. In order to accommodate three control bits, the converter resolution (N) must be set to 13 bits (there are 16 available bits in the JESD204B data word and if three are used for control bits there are 13 bits available for the converter sample - in this example this means there will only be 13 bits available instead of the 14 bits of converter resolution.{{ :resources:eval:ad6674_spi_vdr_bits_adcbase4.png?nolink |}}<WRAP centeralign>//Figure 29. SPIController ADCBase4 Settings for Enabling the Control Bits//</WRAP>   - Next go to the ADCBase4 tab to set up the control bits to select the VDR indicator bits.  In this example three control bits are sent per sample. In order to accommodate three control bits, the converter resolution (N) must be set to 13 bits (there are 16 available bits in the JESD204B data word and if three are used for control bits there are 13 bits available for the converter sample - in this example this means there will only be 13 bits available instead of the 14 bits of converter resolution.{{ :resources:eval:ad6674_spi_vdr_bits_adcbase4.png?nolink |}}<WRAP centeralign>//Figure 29. SPIController ADCBase4 Settings for Enabling the Control Bits//</WRAP>
 ==== Viewing the VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode ==== ==== Viewing the VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode ====
   - The first step is to open a new Logic canvas in VisualAnalog.  In the Logic canvas configure the Input Formatter to set the Resolution to 16 bits and the Alignment to 18 bits.  This will create the space such that all three control bits can be visible in the Logic canvas.{{ :resources:eval:ad6674_va_inputformatter.png?nolink |}}<WRAP centeralign>//Figure 30. Input Formatter Settings for VDR Indicators in the Control Bits//</WRAP>   - The first step is to open a new Logic canvas in VisualAnalog.  In the Logic canvas configure the Input Formatter to set the Resolution to 16 bits and the Alignment to 18 bits.  This will create the space such that all three control bits can be visible in the Logic canvas.{{ :resources:eval:ad6674_va_inputformatter.png?nolink |}}<WRAP centeralign>//Figure 30. Input Formatter Settings for VDR Indicators in the Control Bits//</WRAP>
   - Next configure the Logic Analysis block for the data alignement.  Set the High Bit to 15 and the low bit to 0.  This will align the canvas such that all three control bits can be visible in the Logic canvas.{{ :resources:eval:ad6674_va_logicanalysis.png?nolink |}}<WRAP centeralign>//Figure 31. Logic Analysis Settings for Bit Alignment//</WRAP>   - Next configure the Logic Analysis block for the data alignement.  Set the High Bit to 15 and the low bit to 0.  This will align the canvas such that all three control bits can be visible in the Logic canvas.{{ :resources:eval:ad6674_va_logicanalysis.png?nolink |}}<WRAP centeralign>//Figure 31. Logic Analysis Settings for Bit Alignment//</WRAP>
-  - These settings will create the space in the Logic Canvas display so that all three control bits available in the JESD204B data stream will be visible. {{ :resources:eval:ad6674_va_logiccanvas_cbs_denoted.png?nolink |}}<WRAP centeralign>//Figure 32. Logic Canvas Display Showing Available Control Bits//</WRAP>+  - These settings will create the space in the Logic Canvas display so that all three control bits available in the JESD204B data stream will be visible. (While the example here is for VDR the control bits may be set up to function as Overrange, Signal Monitor (SMON), or Fast Detect (FD) indicators and can be viewed in the output data in a similar manner.) {{ :resources:eval:ad6674_va_logiccanvas_cbs_denoted.png?nolink |}}<WRAP centeralign>//Figure 32. Logic Canvas Display Showing Available Control Bits//</WRAP>
   - Once a signal is input that will trigger VDR to operate the VDR punish bits [1:0] and the VDR High/Low resolution bit can be seen in the Logic Canvas display. In this case control bit 2 is VDR punish bit 1, control bit 1 is VDR punish bit 0, and control bit 0 is the VDR High/Low resolution bit. {{ :resources:eval:ad6674_va_logiccanvas_cbs_denoted_inputsignal.png?nolink |}}<WRAP centeralign>//Figure 33. Logic Canvas Display Showing Control Bits [2:0] Indicating VDR Status//</WRAP>   - Once a signal is input that will trigger VDR to operate the VDR punish bits [1:0] and the VDR High/Low resolution bit can be seen in the Logic Canvas display. In this case control bit 2 is VDR punish bit 1, control bit 1 is VDR punish bit 0, and control bit 0 is the VDR High/Low resolution bit. {{ :resources:eval:ad6674_va_logiccanvas_cbs_denoted_inputsignal.png?nolink |}}<WRAP centeralign>//Figure 33. Logic Canvas Display Showing Control Bits [2:0] Indicating VDR Status//</WRAP>
   - Note that the data alignment from the FPGA to VisualAnalog will fill in the control bits starting from the LSB location in the Logic Canvas display.  In this example data bit two is control bit 2, data bit 1 is control bit 1, and data bit 0 is control bit 0.  If only using control bit 2 then this would reside in the data bit 0 location in the Logic Canvas display. {{ :resources:eval:ad6674_va_logiccanvas_cbs_denoted_cb2only.png?nolink |}}<WRAP centeralign>//Figure 34. Logic Canvas Display Showing Control Bit 2 Only//</WRAP>   - Note that the data alignment from the FPGA to VisualAnalog will fill in the control bits starting from the LSB location in the Logic Canvas display.  In this example data bit two is control bit 2, data bit 1 is control bit 1, and data bit 0 is control bit 0.  If only using control bit 2 then this would reside in the data bit 0 location in the Logic Canvas display. {{ :resources:eval:ad6674_va_logiccanvas_cbs_denoted_cb2only.png?nolink |}}<WRAP centeralign>//Figure 34. Logic Canvas Display Showing Control Bit 2 Only//</WRAP>
resources/eval/ad6674-1000ebz.txt · Last modified: 18 Apr 2024 01:54 by Deferson Romero

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